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-rw-r--r--src/arch/x86/Makefile.inc3
-rw-r--r--src/arch/x86/c_start.S4
-rw-r--r--src/cpu/x86/16bit/entry16.inc2
-rw-r--r--src/cpu/x86/32bit/entry32.inc1
4 files changed, 4 insertions, 6 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 5157564847..00917f0b69 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -98,6 +98,7 @@ bootblock-y += memmove.c
bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c
+bootblock-y += gdt_init.S
bootblock-y += id.S
bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
@@ -160,8 +161,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
romstage-y += boot.c
romstage-y += post.c
-# gdt_init.S is included by entry32.inc when romstage is the first C
-# environment.
romstage-y += gdt_init.S
romstage-y += cpu_common.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index a7af64f9bf..8bebf87435 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -142,10 +142,10 @@ gdtaddr:
/* This is the gdt for GCC part of coreboot.
* It is different from the gdt in ASM part of coreboot
- * which is defined in entry32.inc
+ * which is defined in gdt_init.S
*
* When the machine is initially started, we use a very simple
- * gdt from ROM (that in entry32.inc) which only contains those
+ * gdt from ROM (that in gdt_init.S) which only contains those
* entries we need for protected mode.
*
* When we're executing code from RAM, we want to do more complex
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 2665cc69ae..5e90da1413 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -124,7 +124,7 @@ _start16bit:
ljmpl $ROM_CODE_SEG, $__protected_start
/**
- * The gdt is defined in entry32.inc, it has a 4 Gb code segment
+ * The gdt is defined in gdt_init.S, it has a 4 Gb code segment
* at 0x08, and a 4 GB data segment at 0x10;
*/
__gdtptr:
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 85094483e5..873a809616 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -4,7 +4,6 @@
#include <arch/rom_segs.h>
#include <cpu/x86/post_code.h>
-#include <arch/x86/gdt_init.S>
.code32
/*