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-rw-r--r--src/mainboard/google/hatch/variants/duffy/overridetree.cb35
-rw-r--r--src/mainboard/google/hatch/variants/kaisa/overridetree.cb35
2 files changed, 38 insertions, 32 deletions
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
index 72f9516b3f..6bb1d94a69 100644
--- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
@@ -1,6 +1,11 @@
chip soc/intel/cannonlake
register "tcc_offset" = "5" # TCC of 95C
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 51,
+ }"
+
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -271,29 +276,27 @@ chip soc/intel/cannonlake
chip drivers/intel/dptf
## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU,
- .thresholds={TEMP_PCT(90, 85),
- TEMP_PCT(85, 75),
- TEMP_PCT(80, 65),
- TEMP_PCT(75, 55),
- TEMP_PCT(70, 45),}}"
+ .thresholds={TEMP_PCT(94, 0),}}"
register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
- .thresholds={TEMP_PCT(50, 85),
- TEMP_PCT(47, 75),
- TEMP_PCT(45, 65),
- TEMP_PCT(42, 55),
- TEMP_PCT(39, 45),}}"
+ .thresholds={TEMP_PCT(65, 90),
+ TEMP_PCT(61, 80),
+ TEMP_PCT(57, 70),
+ TEMP_PCT(53, 60),
+ TEMP_PCT(49, 50),
+ TEMP_PCT(45, 40),
+ TEMP_PCT(41, 0),}}"
## Passive Policy
- register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)"
- register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
+ register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
+ register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)"
## Critical Policy
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
- register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
+ register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
## Power Limits Control
# PL1 is fixed at 15W, avg over 28-32s interval
- # 25-64W PL2 in 1000mW increments, avg over 28-32s interval
+ # 15-51W PL2 in 1000mW increments, avg over 28-32s interval
register "controls.power_limits.pl1" = "{
.min_power = 15000,
.max_power = 15000,
@@ -301,8 +304,8 @@ chip soc/intel/cannonlake
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
- .min_power = 25000,
- .max_power = 64000,
+ .min_power = 15000,
+ .max_power = 51000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index 5fc9c0811b..e3dcbd5f87 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -1,6 +1,11 @@
chip soc/intel/cannonlake
register "tcc_offset" = "5" # TCC of 95C
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 51,
+ }"
+
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -271,29 +276,27 @@ chip soc/intel/cannonlake
chip drivers/intel/dptf
## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU,
- .thresholds={TEMP_PCT(90, 85),
- TEMP_PCT(85, 75),
- TEMP_PCT(80, 65),
- TEMP_PCT(75, 55),
- TEMP_PCT(70, 45),}}"
+ .thresholds={TEMP_PCT(94, 0),}}"
register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
- .thresholds={TEMP_PCT(50, 85),
- TEMP_PCT(47, 75),
- TEMP_PCT(45, 65),
- TEMP_PCT(42, 55),
- TEMP_PCT(39, 45),}}"
+ .thresholds={TEMP_PCT(65, 90),
+ TEMP_PCT(61, 80),
+ TEMP_PCT(57, 70),
+ TEMP_PCT(53, 60),
+ TEMP_PCT(49, 50),
+ TEMP_PCT(45, 40),
+ TEMP_PCT(41, 0),}}"
## Passive Policy
- register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)"
- register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
+ register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
+ register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)"
## Critical Policy
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
- register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
+ register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
## Power Limits Control
# PL1 is fixed at 15W, avg over 28-32s interval
- # 25-64W PL2 in 1000mW increments, avg over 28-32s interval
+ # 15-51W PL2 in 1000mW increments, avg over 28-32s interval
register "controls.power_limits.pl1" = "{
.min_power = 15000,
.max_power = 15000,
@@ -301,8 +304,8 @@ chip soc/intel/cannonlake
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
- .min_power = 25000,
- .max_power = 64000,
+ .min_power = 15000,
+ .max_power = 51000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"