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-rw-r--r--src/northbridge/intel/i440bx/i440bx.h2
-rw-r--r--src/northbridge/intel/i440bx/raminit.c10
2 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h
index 4724719cfd..6e93e83d1a 100644
--- a/src/northbridge/intel/i440bx/i440bx.h
+++ b/src/northbridge/intel/i440bx/i440bx.h
@@ -86,4 +86,6 @@
#define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
#define BUFFC 0xf0 /* Buffer Control Register (0x0000). */
+#define NB PCI_DEV(0, 0, 0)
+
#endif /* NORTHBRIDGE_INTEL_I440BX_I440BX_H */
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 86e9595107..67d8d3f334 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
- * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ * Copyright (C) 2010,2017 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -25,11 +25,9 @@
#include "i440bx.h"
#include "raminit.h"
-/*-----------------------------------------------------------------------------
-Macros and definitions.
------------------------------------------------------------------------------*/
-
-#define NB PCI_DEV(0, 0, 0)
+/*
+ * Macros and definitions
+ */
/* Debugging macros. */
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)