diff options
| -rw-r--r-- | src/mainboard/google/volteer/fw_config.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 21 |
2 files changed, 28 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 4067fa526a..50e8f93080 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -66,6 +66,10 @@ static const struct pad_config i2s_disable_pads[] = { PAD_NC(GPP_R7, NONE), }; +static const struct pad_config sd_gl9755s_pads[] = { + PAD_CFG_GPO(GPP_D16, 1, DEEP), +}; + static void fw_config_handle(void *unused) { if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { @@ -94,5 +98,9 @@ static void fw_config_handle(void *unused) gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } + if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S))) { + printk(BIOS_INFO, "Configure GPIOs for SD GL9755S.\n"); + gpio_configure_pads(sd_gl9755s_pads, ARRAY_SIZE(sd_gl9755s_pads)); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 50be7367da..fa807ba40f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -445,7 +445,26 @@ chip soc/intel/tigerlake device ref sata on end device ref pcie_rp1 on end device ref pcie_rp7 on end - device ref pcie_rp8 on end + device ref pcie_rp8 on + probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5261 + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" + register "srcclk_pin" = "3" + device generic 0 on + probe DB_SD SD_GL9755S + end + end + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" + register "srcclk_pin" = "3" + register "is_external" = "1" + device generic 1 on + probe DB_SD SD_RTS5261 + end + end + end device ref pcie_rp9 on end device ref pcie_rp11 on end device ref uart0 on end |