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-rw-r--r--src/mainboard/asrock/b85m_pro4/devicetree.cb8
-rw-r--r--src/mainboard/asrock/h81m-hds/devicetree.cb9
-rw-r--r--src/mainboard/google/beltino/devicetree.cb9
-rw-r--r--src/mainboard/google/slippy/devicetree.cb9
-rw-r--r--src/mainboard/intel/baskingridge/devicetree.cb9
-rw-r--r--src/mainboard/lenovo/t440p/devicetree.cb8
-rw-r--r--src/mainboard/supermicro/x10slm-f/devicetree.cb9
-rw-r--r--src/southbridge/intel/lynxpoint/chip.h13
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c30
9 files changed, 16 insertions, 88 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb
index b724652ea6..106df54e01 100644
--- a/src/mainboard/asrock/b85m_pro4/devicetree.cb
+++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb
@@ -27,14 +27,6 @@ chip northbridge/intel/haswell
chip southbridge/intel/lynxpoint
register "gen1_dec" = "0x000c0291" # Super I/O HWM
- register "pirqa_routing" = "0x80"
- register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x80"
- register "pirqd_routing" = "0x80"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
register "sata_ahci" = "1"
register "sata_port_map" = "0x3f"
diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb
index 561c1e35d5..8f368961de 100644
--- a/src/mainboard/asrock/h81m-hds/devicetree.cb
+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb
@@ -35,15 +35,6 @@ chip northbridge/intel/haswell
end
chip southbridge/intel/lynxpoint
- register "pirqa_routing" = "0x80"
- register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x80"
- register "pirqd_routing" = "0x80"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
register "sata_ahci" = "1"
register "sata_port_map" = "0x33"
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index 171b93f81d..8fdfbd79a0 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -36,15 +36,6 @@ chip northbridge/intel/haswell
device pci 03.0 on end # mini-hd audio
chip southbridge/intel/lynxpoint
- register "pirqa_routing" = "0x80"
- register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x80"
- register "pirqd_routing" = "0x80"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index bbb22ca9f0..200721b8ef 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -40,15 +40,6 @@ chip northbridge/intel/haswell
device pci 03.0 on end # mini-hd audio
chip southbridge/intel/lynxpoint
- register "pirqa_routing" = "0x80"
- register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x80"
- register "pirqd_routing" = "0x80"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb
index 8ea8e97c61..6345090c7a 100644
--- a/src/mainboard/intel/baskingridge/devicetree.cb
+++ b/src/mainboard/intel/baskingridge/devicetree.cb
@@ -32,15 +32,6 @@ chip northbridge/intel/haswell
device pci 02.0 on end # vga controller
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
- register "pirqa_routing" = "0x80"
- register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x80"
- register "pirqd_routing" = "0x80"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb
index e8f8a1a396..60728c496c 100644
--- a/src/mainboard/lenovo/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/t440p/devicetree.cb
@@ -38,14 +38,6 @@ chip northbridge/intel/haswell
register "gen4_dec" = "0x000c06a1"
register "gpi13_routing" = "2"
register "gpi1_routing" = "2"
- register "pirqa_routing" = "0x80"
- register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x80"
- register "pirqd_routing" = "0x80"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
register "sata_ahci" = "1"
# 0(HDD), 1(M.2), 5(ODD)
register "sata_port_map" = "0x23"
diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb
index 80e79d8682..ffcc56d15c 100644
--- a/src/mainboard/supermicro/x10slm-f/devicetree.cb
+++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb
@@ -26,15 +26,6 @@ chip northbridge/intel/haswell
device pci 03.0 off end # Mini-HD audio
chip southbridge/intel/lynxpoint
- register "pirqa_routing" = "0x80"
- register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x80"
- register "pirqd_routing" = "0x80"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
register "sata_ahci" = "1"
register "sata_port_map" = "0x3f"
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index ed362a2d65..cba7671ecc 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -7,19 +7,6 @@
struct southbridge_intel_lynxpoint_config {
/**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
-
- /**
* GPI Routing configuration for LynxPoint-H
*
* Only the lower two bits have a meaning:
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 7082a79d31..898d6f0986 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -96,18 +96,18 @@ static void pch_enable_serial_irqs(struct device *dev)
static void pch_pirq_init(struct device *dev)
{
struct device *irq_dev;
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+ const uint8_t pirq = 0x80;
+
+ pci_write_config8(dev, PIRQA_ROUT, pirq);
+ pci_write_config8(dev, PIRQB_ROUT, pirq);
+ pci_write_config8(dev, PIRQC_ROUT, pirq);
+ pci_write_config8(dev, PIRQD_ROUT, pirq);
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+ pci_write_config8(dev, PIRQE_ROUT, pirq);
+ pci_write_config8(dev, PIRQF_ROUT, pirq);
+ pci_write_config8(dev, PIRQG_ROUT, pirq);
+ pci_write_config8(dev, PIRQH_ROUT, pirq);
/* Eric Biederman once said we should let the OS do this.
* I am not so sure anymore he was right.
@@ -122,10 +122,12 @@ static void pch_pirq_init(struct device *dev)
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ case 1: /* INTA# */
+ case 2: /* INTB# */
+ case 3: /* INTC# */
+ case 4: /* INTD# */
+ int_line = pirq;
+ break;
}
if (!int_line)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 07:56:42 +0000