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-rw-r--r--src/mainboard/amd/inagua/OemCustomize.c24
-rw-r--r--src/mainboard/amd/parmer/OemCustomize.c43
-rw-r--r--src/mainboard/amd/persimmon/OemCustomize.c30
-rw-r--r--src/mainboard/amd/south_station/OemCustomize.c30
-rw-r--r--src/mainboard/amd/thatcher/OemCustomize.c42
-rw-r--r--src/mainboard/amd/torpedo/OemCustomize.c36
-rw-r--r--src/mainboard/amd/union_station/OemCustomize.c30
-rw-r--r--src/mainboard/asrock/e350m1/OemCustomize.c12
-rw-r--r--src/mainboard/asus/f2a85-m/OemCustomize.c18
-rw-r--r--src/mainboard/elmex/pcm205400/OemCustomize.c30
-rw-r--r--src/mainboard/gizmosphere/gizmo/OemCustomize.c30
-rw-r--r--src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c43
-rw-r--r--src/mainboard/lenovo/g505s/OemCustomize.c43
-rw-r--r--src/mainboard/lippert/frontrunner-af/OemCustomize.c30
-rw-r--r--src/mainboard/lippert/toucan-af/OemCustomize.c30
-rw-r--r--src/mainboard/msi/ms7721/OemCustomize.c30
-rw-r--r--src/mainboard/pcengines/apu1/OemCustomize.c30
17 files changed, 440 insertions, 91 deletions
diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c
index 5fc293b791..fa2d7e4b51 100644
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ b/src/mainboard/amd/inagua/OemCustomize.c
@@ -23,25 +23,41 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 4)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 6)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 7)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c
index 21847f91a7..0a0fe7545e 100644
--- a/src/mainboard/amd/parmer/OemCustomize.c
+++ b/src/mainboard/amd/parmer/OemCustomize.c
@@ -69,48 +69,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
};
@@ -131,7 +159,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
- /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
},
};
diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c
index a666de098f..a646e38691 100644
--- a/src/mainboard/amd/persimmon/OemCustomize.c
+++ b/src/mainboard/amd/persimmon/OemCustomize.c
@@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 46)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 46)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 46)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c
index c90feb1d02..45c9f11d57 100644
--- a/src/mainboard/amd/south_station/OemCustomize.c
+++ b/src/mainboard/amd/south_station/OemCustomize.c
@@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 4)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 5)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 6)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 7)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c
index c035722c58..a6c98b9026 100644
--- a/src/mainboard/amd/thatcher/OemCustomize.c
+++ b/src/mainboard/amd/thatcher/OemCustomize.c
@@ -69,48 +69,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 15, 8),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 4, PCI Device Number 4, LAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 7, PCI Device Number 7, Disabled */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
};
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
index bb377fa3c6..1ad6cde9db 100644
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ b/src/mainboard/amd/torpedo/OemCustomize.c
@@ -22,37 +22,61 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, BIT2)
},
// Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 19),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, BIT3)
},
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
}
};
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
index 43b2521097..d266d277f0 100644
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ b/src/mainboard/amd/union_station/OemCustomize.c
@@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 4)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 5)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 6)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 7)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c
index bf928d252d..5e699afcd5 100644
--- a/src/mainboard/asrock/e350m1/OemCustomize.c
+++ b/src/mainboard/asrock/e350m1/OemCustomize.c
@@ -23,13 +23,21 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 954268f73f..6aabe73f8a 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -69,19 +69,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
};
diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c
index 05f2807ece..6cc52e8a86 100644
--- a/src/mainboard/elmex/pcm205400/OemCustomize.c
+++ b/src/mainboard/elmex/pcm205400/OemCustomize.c
@@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 46)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 46)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 46)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
index 86c341624f..8dea73284f 100644
--- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
@@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 4)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 5)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 6)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 7)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
index d0fe4017a8..44c2c38674 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
@@ -70,48 +70,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
};
@@ -132,7 +160,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
- /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
},
};
diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c
index aaed339e96..7e4fa6e82f 100644
--- a/src/mainboard/lenovo/g505s/OemCustomize.c
+++ b/src/mainboard/lenovo/g505s/OemCustomize.c
@@ -70,48 +70,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
};
@@ -132,7 +160,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
- /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
},
};
diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c
index 02ef6de0db..7c6dc3380d 100644
--- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c
+++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c
@@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c
index 0bab96ff23..ea4c5af278 100644
--- a/src/mainboard/lippert/toucan-af/OemCustomize.c
+++ b/src/mainboard/lippert/toucan-af/OemCustomize.c
@@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c
index 80e6c96751..5377e8842d 100644
--- a/src/mainboard/msi/ms7721/OemCustomize.c
+++ b/src/mainboard/msi/ms7721/OemCustomize.c
@@ -71,31 +71,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
};
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
index ab21b33a0d..330531f7e4 100644
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ b/src/mainboard/pcengines/apu1/OemCustomize.c
@@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 4)
},
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 5)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 6)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 7)
},
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1, 0)
}
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 13:20:18 +0000