diff options
| -rw-r--r-- | src/mainboard/hp/dl145_g1/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/hp/dl145_g1/acpi_tables.c | 5 | ||||
| -rw-r--r-- | src/mainboard/hp/dl145_g1/romstage.c | 33 |
3 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 94189ce4f6..2768007fbc 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select SET_FIDVID + select SET_FIDVID_DEBUG select RAMINIT_SYSINFO # select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c index dd96318f58..c94688ec1a 100644 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -21,6 +21,7 @@ #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/acpi.h" #include "mb_sysconf.h" +#include <cpu/amd/model_fxx_powernow.h> #define DUMP_ACPI_TABLES 0 @@ -163,6 +164,10 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); +#if CONFIG_SET_FIDVID + amd_model_fxx_generate_powernow(pm_base + 0x10, 6, 1); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); +#endif return (unsigned long) (acpigen_get_current()); } diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 67ce9c1f01..94771ddb9b 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -82,6 +82,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" +#if CONFIG_SET_FIDVID +#include "cpu/amd/model_fxx/fidvid.c" +#endif #define RC0 ((1<<1)<<8) #define RC1 ((1<<2)<<8) @@ -126,6 +129,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif ht_setup_chains_x(sysinfo); +#if CONFIG_SET_FIDVID + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + struct cpuid_result cpuid1 = cpuid(0x80000007); + if ((cpuid1.edx & 0x6) == 0x6) { + { + /* Read FIDVID_STATUS */ + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + + } else { + print_debug("Changing FIDVID not supported\n"); + } +#endif needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); @@ -155,6 +185,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); +#if CONFIG_SET_FIDVID + init_timer(); // Need to use TMICT to synchronize FID/VID +#endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices(); |