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diff --git a/Documentation/mainboard/dell/latitude_e7240.md b/Documentation/mainboard/dell/latitude_e7240.md new file mode 100644 index 0000000000..2d2c48ae6d --- /dev/null +++ b/Documentation/mainboard/dell/latitude_e7240.md @@ -0,0 +1,79 @@ +# Dell Latitude E7240 + +This page is about the notebook [Dell Latitude E7240]. + +## Release status + +Dell Latitude E7240 was released in 2013 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: +1. mrc.bin +2. Intel ME firmware + +Memory reference code in mrc.bin is used to initialize the Haswell platform. +You need this blob to build a working coreboot image. Please read +[mrc.bin](../../northbridge/intel/haswell/mrc.bin) for instructions on +retrieving and using it. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. +It can be extracted from the OEM firmware. You can also flash only the BIOS +region to leave Intel ME firmware untouched. + +## Programming + +To flash with a programmer, you need to remove the battery and the base cover. + +For more details have a look at the general [flashing tutorial]. + +It is also possible to flash internally with flashrom when the IFD is unlocked. + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is next to the miniDP port. + +There's a serial port on dock, but it's not supported yet in coreboot. + +Schematic of this laptop can be found on [Lab One]. The board name is Compal LA-9431P. + +## Test status + +### Not working + +- EC ACPI +- Touchpad and the buttons on it +- SD/MMC card reader (kernel reports "Timeout waiting for hardware cmd interrupt.") +- No internal display before booting to OS when connected with a dock + +### Working + +- Integrated graphics init with libgfxinit +- mSATA +- WLAN +- USB +- Keyboard +- Dock: all USB ports, DisplayPort, eSATA +- Internal flashing when IFD is unlocked + + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell-ULT | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point Low Power | ++------------------+-----------------------------+ +| EC | SMSC MEC5075 | ++------------------+-----------------------------+ +| Super I/O | SMSC ECE5048 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[Dell Latitude E7240]: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7240-ultrabook/docs +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[Lab One]: https://www.laboneinside.com/dell-latitude-e7240-schematic-diagram/ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1f8f6bc26e..d16eaba127 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -32,6 +32,7 @@ This section contains documentation about coreboot on specific mainboards. ## Dell +- [Latitude E7240](dell/latitude_e7240.md) - [OptiPlex 9010 SFF](dell/optiplex_9010.md) ## Emulation diff --git a/src/mainboard/dell/latitude_e7240/Kconfig b/src/mainboard/dell/latitude_e7240/Kconfig new file mode 100644 index 0000000000..2e3b4b4a07 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/Kconfig @@ -0,0 +1,37 @@ +if BOARD_DELL_LATITUDE_E7240 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_DELL_MEC5055 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "dell/latitude_e7240" + +config MAINBOARD_PART_NUMBER + string + default "Latitude E7240" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +config VGA_BIOS_ID + string + default "8086,0a16" + +config USBDEBUG_HCD_INDEX + int + default 1 + +endif diff --git a/src/mainboard/dell/latitude_e7240/Kconfig.name b/src/mainboard/dell/latitude_e7240/Kconfig.name new file mode 100644 index 0000000000..83ab9358a5 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_LATITUDE_E7240 + bool "Latitude E7240" diff --git a/src/mainboard/dell/latitude_e7240/Makefile.inc b/src/mainboard/dell/latitude_e7240/Makefile.inc new file mode 100644 index 0000000000..ec8ca220a5 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/latitude_e7240/acpi/ec.asl b/src/mainboard/dell/latitude_e7240/acpi/ec.asl new file mode 100644 index 0000000000..24915c22ef --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/acpi/ec.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* FIXME: not working yet */ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 39) + + Method (_Q66, 0, NotSerialized) + { + Store ("EC: _Q66", Debug) + } +} diff --git a/src/mainboard/dell/latitude_e7240/acpi/platform.asl b/src/mainboard/dell/latitude_e7240/acpi/platform.asl new file mode 100644 index 0000000000..2d24bbd9b9 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/acpi/platform.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/dell/latitude_e7240/acpi/superio.asl b/src/mainboard/dell/latitude_e7240/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/latitude_e7240/acpi_tables.c b/src/mainboard/dell/latitude_e7240/acpi_tables.c new file mode 100644 index 0000000000..5c018f174b --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/latitude_e7240/board_info.txt b/src/mainboard/dell/latitude_e7240/board_info.txt new file mode 100644 index 0000000000..46e950abbd --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7240-ultrabook/docs +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: n +Release year: 2013 diff --git a/src/mainboard/dell/latitude_e7240/bootblock.c b/src/mainboard/dell/latitude_e7240/bootblock.c new file mode 100644 index 0000000000..62f7fc2aa0 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/bootblock.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <ec/dell/mec5055/mec5055.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + /* port 0x910 and 0x911 is needed to initialize the EC */ + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x007c0901); + mec5055_early_init(); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x005c0921); +} diff --git a/src/mainboard/dell/latitude_e7240/devicetree.cb b/src/mainboard/dell/latitude_e7240/devicetree.cb new file mode 100644 index 0000000000..9395347bd9 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/devicetree.cb @@ -0,0 +1,75 @@ +chip northbridge/intel/haswell + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "0" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "2" + register "c1_battery" = "2" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "9" + register "c3_battery" = "9" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x1028 0x05ca inherit + + device pci 00.0 on end # Host bridge + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x005c0921" + register "gen3_dec" = "0x003c07e1" + + register "alt_gp_smi_en" = "0x00002000" + register "gpe0_en_1" = "0x00000100" + register "gpe0_en_2" = "0x00000080" + register "gpe0_en_4" = "0x00000042" + + # 0(eSATA on dock), 1(mSATA near the fan), 3(mSATA near WLAN) + register "sata_port_map" = "0x0b" + + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 on end # PCIe Port #5, SD/MMC Card Reader + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/dell/latitude_e7240/dsdt.asl b/src/mainboard/dell/latitude_e7240/dsdt.asl new file mode 100644 index 0000000000..b5343726ff --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/latitude_e7240/gma-mainboard.ads b/src/mainboard/dell/latitude_e7240/gma-mainboard.ads new file mode 100644 index 0000000000..cdc7f18680 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, + HDMI1, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/latitude_e7240/gpio.c b/src/mainboard/dell/latitude_e7240/gpio.c new file mode 100644 index 0000000000..52a108d29f --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/gpio.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_NATIVE, + [5] = LP_GPIO_NATIVE, + [6] = LP_GPIO_NATIVE, + [7] = LP_GPIO_NATIVE, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_LOW, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_LOW, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [79] = LP_GPIO_OUT_LOW, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/latitude_e7240/hda_verb.c b/src/mainboard/dell/latitude_e7240/hda_verb.c new file mode 100644 index 0000000000..7fd135a611 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805ca, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805ca), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x01a19030), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/latitude_e7240/mainboard.c b/src/mainboard/dell/latitude_e7240/mainboard.c new file mode 100644 index 0000000000..98cc8110cc --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/latitude_e7240/romstage.c b/src/mainboard/dell/latitude_e7240/romstage.c new file mode 100644 index 0000000000..7b69b1c159 --- /dev/null +++ b/src/mainboard/dell/latitude_e7240/romstage.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa4; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* dock left */ + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, /* right, EHCI debug */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, /* back right, dock back */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, /* WWAN */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, 1 }, /* right */ + { 1, 0 }, /* back left */ + { 1, 2 }, /* back right, dock back */ + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} |