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diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 11f964f34d..970f18f007 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -71,6 +71,10 @@ The boards in this section are not real mainboards, but emulators. - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +## Libretrend + +- [LT1000](libretrend/lt1000.md) + ### Nehalem series - [T410](lenovo/t410.md) diff --git a/Documentation/mainboard/libretrend/lt1000.jpg b/Documentation/mainboard/libretrend/lt1000.jpg Binary files differnew file mode 100644 index 0000000000..c450c4add3 --- /dev/null +++ b/Documentation/mainboard/libretrend/lt1000.jpg diff --git a/Documentation/mainboard/libretrend/lt1000.md b/Documentation/mainboard/libretrend/lt1000.md new file mode 100644 index 0000000000..78d5fc056c --- /dev/null +++ b/Documentation/mainboard/libretrend/lt1000.md @@ -0,0 +1,117 @@ +# Libretrend LT1000 + +This page describes how to run coreboot on the [Libretrend LT1000] (aka +Librebox). + + + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done +automatically by coreboot build system and included into the image) from the +*3rdparty/fsp* submodule. + +Microcode updates are automatically included into the coreboot image by build +system from the *3rdparty/intel-microcode* submodule. + +The mainboard code also contains a VBT file (version 1.00, BDB version 2.09) +which is automatically included into the image by coreboot build system. + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. It is strongly advised to +flash only the BIOS region if not having an external programmer, see known +issues. + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located on the top middle side of the board near the CPU fan, +between the DIMM slots and the M.2 disk. Use a clip (or solder the wires) to +program the chip. Specifically, it's a Winbond W25Q64FV (3.3V) - +[datasheet][W25Q64FV]. + +## Known issues + +- Fastboot (MRC cache) is not working reliably (missing schematics for CPU to + DIMM wiring). +- Flashing ME region with already cleaned ME firmware may lead to platform not + booting, flashing full ME firmware is needed to recover. +- In order to have the USB device wake support from S3 state using the front + USB 3.0 ports, one has to move the jumper on DUSB1_PWR_SET header (it will + switch the power rails for the USB 3.0 ports). +- There are 6 unknown GPIO pins on the board. + +## Untested + +Not all mainboard's peripherals and functions were tested because of lack of +the cables or not being populated on the board case. + +- LVDS header +- Onboard USB 2.0 and USB 3.0 headers +- Speakers and mic header +- SPDIF header +- Audio header +- PS/2 header +- LPT header +- CIR (infrared header) +- COM2 port RS485 mode (RS232/RS485 mode is controlled via jumper) +- SYS_FAN header + +## Working + +- USB +- Ethernet +- Integrated graphics (with libgfxinit) on VGA and HDMI ports +- flashrom +- PCIe +- NVMe +- WiFi and Bluetooth +- SATA +- Serial ports 1-6 +- SMBus +- HDA (verbs not implemented yet, but works under GNU/Linux (4.15 tested)) +- Initialization with KBL FSP 2.0 +- SeaBIOS payload (version rel-1.13.0) +- TPM2 ([custom module] connected to LPC DEBUG header) +- Automatic fan control +- Platform boots with cleaned ME (MFS partition must be left on SPI flash) + +## Technology + +The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not +sold yet). More details on [baseboard site]. Unfortunately the board manual is +not publicly available. + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Core i7-6500U | ++------------------+--------------------------------------------------+ +| PCH | Skylake-U Premium | ++------------------+--------------------------------------------------+ +| Super I/O | ITE IT8786E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[Libretrend LT1000]: https://libretrend.com/specs/librebox/ +[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom +[baseboard site]: http://www.minicase.net/product_LR-i7S65T1.html +[custom module]: https://shop.3mdeb.com/product/tpm2-module-for-librebox/ diff --git a/MAINTAINERS b/MAINTAINERS index a79d98f01c..3a31847c9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -317,6 +317,12 @@ M: Vlado Cibic <vladocb@protonmail.com> S: Maintained F: src/mainboard/asus/p8z77-m_pro/ +LIBRETREND LT1000 MAINBOARD +M: Piotr Król <piotr.krol@3mdeb.com> +M: Michał Żygowski <michal.zygowski@3mdeb.com> +S: Maintained +F: src/mainboard/libretrend/lt1000 + PC ENGINES ALL MAINBOARDS M: Piotr Król <piotr.krol@3mdeb.com> M: Michał Żygowski <michal.zygowski@3mdeb.com> diff --git a/configs/config.libretrend_lt1000 b/configs/config.libretrend_lt1000 new file mode 100644 index 0000000000..f12ae3f81c --- /dev/null +++ b/configs/config.libretrend_lt1000 @@ -0,0 +1,5 @@ +CONFIG_VENDOR_LIBRETREND=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_USER_TPM2=y +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y diff --git a/src/mainboard/libretrend/Kconfig b/src/mainboard/libretrend/Kconfig new file mode 100644 index 0000000000..7e1eacdd71 --- /dev/null +++ b/src/mainboard/libretrend/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_LIBRETREND + +choice + prompt "Mainboard model" + +source "src/mainboard/libretrend/*/Kconfig.name" + +endchoice + +source "src/mainboard/libretrend/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Libretrend" + +endif # VENDOR_LIBRETREND diff --git a/src/mainboard/libretrend/Kconfig.name b/src/mainboard/libretrend/Kconfig.name new file mode 100644 index 0000000000..cd272b0a31 --- /dev/null +++ b/src/mainboard/libretrend/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_LIBRETREND + bool "Libretrend" diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig new file mode 100644 index 0000000000..b4a4e49ef7 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/Kconfig @@ -0,0 +1,55 @@ +if BOARD_LIBRETREND_LT1000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_SKYLAKE + select SPD_READ_BY_WORD + select SUPERIO_ITE_IT8786E + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_PART_NUMBER + string + default "LT1000" + +config MAINBOARD_DIR + string + default "libretrend/lt1000" + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,1916" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CBFS_SIZE + hex + default 0x600000 + +config ADD_FSP_BINARIES + bool + default y + +config FSP_USE_REPO + bool + default y + +endif diff --git a/src/mainboard/libretrend/lt1000/Kconfig.name b/src/mainboard/libretrend/lt1000/Kconfig.name new file mode 100644 index 0000000000..26e5255f05 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LIBRETREND_LT1000 + bool "LT1000" diff --git a/src/mainboard/libretrend/lt1000/Makefile.inc b/src/mainboard/libretrend/lt1000/Makefile.inc new file mode 100644 index 0000000000..cab4a5e194 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This file is part of the coreboot project. + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/libretrend/lt1000/acpi/ec.asl b/src/mainboard/libretrend/lt1000/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/acpi/ec.asl diff --git a/src/mainboard/libretrend/lt1000/acpi/superio.asl b/src/mainboard/libretrend/lt1000/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/acpi/superio.asl diff --git a/src/mainboard/libretrend/lt1000/board_info.txt b/src/mainboard/libretrend/lt1000/board_info.txt new file mode 100644 index 0000000000..2d7c8933e3 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Libretrend +Board name: LT1000 +Category: desktop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2018 diff --git a/src/mainboard/libretrend/lt1000/bootblock.c b/src/mainboard/libretrend/lt1000/bootblock.c new file mode 100644 index 0000000000..bc85deca9b --- /dev/null +++ b/src/mainboard/libretrend/lt1000/bootblock.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8786e/it8786e.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO) +#define SERIAL1_DEV PNP_DEV(0x2e, IT8786E_SP1) +#define SERIAL3_DEV PNP_DEV(0x2e, IT8786E_SP3) +#define SERIAL4_DEV PNP_DEV(0x2e, IT8786E_SP4) +#define SERIAL5_DEV PNP_DEV(0x2e, IT8786E_SP5) +#define SERIAL6_DEV PNP_DEV(0x2e, IT8786E_SP6) + +void bootblock_mainboard_early_init(void) +{ + ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_3vsbsw(GPIO_DEV); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); + + /* + * FIXME: + * IT8786E has 6 COM ports, COM1/3/5 have default IO base 0x3f8 and + * COM2/4/6 have 0x2f8. When enabling devices before setting resources + * from devicetree, the output on debugging COM1 becomes very slow due + * to the same IO bases for multiple COM ports. For now set different + * hardcoded IO bases for COM3/4/5/6 ports, they will be set later to + * desired values from devicetree. They can be also turned off. + */ + ite_enable_serial(SERIAL3_DEV, 0x3e8); + ite_enable_serial(SERIAL4_DEV, 0x2e8); + ite_enable_serial(SERIAL5_DEV, 0x2f0); + ite_enable_serial(SERIAL6_DEV, 0x2e0); +} diff --git a/src/mainboard/libretrend/lt1000/data.vbt b/src/mainboard/libretrend/lt1000/data.vbt Binary files differnew file mode 100644 index 0000000000..cb4a2f4a6c --- /dev/null +++ b/src/mainboard/libretrend/lt1000/data.vbt diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb new file mode 100644 index 0000000000..f54b877f18 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -0,0 +1,298 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Set the Thermal Control Circuit (TCC) activation value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f + register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef + register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff + register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------------+-------+ + #| Domain/Setting | SA | IA | GT-Unsliced | GT | + #+----------------+-------+-------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" + register "PcieRpClkSrcNumber[8]" = "3" + register "PcieRpClkSrcNumber[9]" = "3" + register "PcieRpClkSrcNumber[10]" = "3" + register "PcieRpClkSrcNumber[11]" = "3" + + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" + end + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "SSD_M.2 2242/2280" "SlotDataBusWidth4X" + end + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip superio/ite/it8786e + register "TMPIN1.mode" = "THERMAL_PECI" + register "TMPIN1.offset" = "100" + register "TMPIN1.min" = "128" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN2.min" = "128" + register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" + register "ec.vin_mask" = "VIN_ALL" + # FAN1 is CPU fan (on board) + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = " 1" + register "FAN1.smart.tmp_off" = "35" + register "FAN1.smart.tmp_start" = "60" + register "FAN1.smart.tmp_full" = "85" + register "FAN1.smart.tmp_delta" = " 2" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "24" + # FAN2 is system fan (4 pin connector populated) + #register "FAN2.mode" = "FAN_MODE_OFF" + # FAN3 PWM is used for LVDS backlight control + #register "FAN3.mode" = "FAN_MODE_OFF" + + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Printer Port + io 0x60 = 0x378 + io 0x62 = 0x778 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa40 + io 0x62 = 0xa30 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO + end + device pnp 2e.8 on # COM 3 + io 0x60 = 0x3e8 + irq 0x70 = 3 + end + device pnp 2e.9 on # COM 4 + io 0x60 = 0x2e8 + irq 0x70 = 4 + end + device pnp 2e.a off end # CIR + device pnp 2e.b on # COM 5 + io 0x60 = 0x2f0 + irq 0x70 = 3 + end + device pnp 2e.c on # COM 6 + io 0x60 = 0x2e0 + irq 0x70 = 4 + end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl new file mode 100644 index 0000000000..624806ca04 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/libretrend/lt1000/gma-mainboard.ads b/src/mainboard/libretrend/lt1000/gma-mainboard.ads new file mode 100644 index 0000000000..210ea288b8 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI2, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/libretrend/lt1000/gpio.h b/src/mainboard/libretrend/lt1000/gpio.h new file mode 100644 index 0000000000..d937ae5945 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/gpio.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef LT1000_GPIO_H +#define LT1000_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +/* PME# */ PAD_CFG_NC(GPP_A11), +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP), +/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP), +/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* VRALERT# */ PAD_CFG_NC(GPP_B2), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), +/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), +/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), +/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), +/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP), +/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */ +/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NC(GPP_C12), +/* UART1_TXD */ PAD_CFG_NC(GPP_C13), +/* UART1_RTS# */ PAD_CFG_NC(GPP_C14), +/* UART1_CTS# */ PAD_CFG_NC(GPP_C15), +/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP), +/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP), +/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* UART2_RXD */ PAD_CFG_NC(GPP_C20), +/* UART2_TXD */ PAD_CFG_NC(GPP_C21), +/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), +/* UART2_CTS# */ PAD_CFG_NC(GPP_C23), + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), +/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), +/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP), +/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), +/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP), +/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), +/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), + +/* SATAXPCI0 */ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), +/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), + +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), +/* I2C5_SDA */ PAD_CFG_NC(GPP_F10), +/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), +/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), +/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), +/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), +/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), +/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), +/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), +/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), +/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), +/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), +/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), + +/* BATLOW# */ PAD_CFG_NC(GPD0), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), +/* LAN_WAKE# */ PAD_CFG_NC(GPD2), +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +#endif + +#endif diff --git a/src/mainboard/libretrend/lt1000/ramstage.c b/src/mainboard/libretrend/lt1000/ramstage.c new file mode 100644 index 0000000000..e9eb80afa2 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* + * Configure pads prior to SiliconInit() in case there are any + * dependencies during hardware initialization. + */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/libretrend/lt1000/romstage.c b/src/mainboard/libretrend/lt1000/romstage.c new file mode 100644 index 0000000000..510038b3b7 --- /dev/null +++ b/src/mainboard/libretrend/lt1000/romstage.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + const u8 dqs_map[2][8] = { + { 0, 1, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} |
