diff options
| -rw-r--r-- | src/mainboard/asrock/e350m1/BiosCallOuts.c | 8 | ||||
| -rw-r--r-- | src/mainboard/asrock/e350m1/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/asrock/e350m1/devicetree.cb | 36 | ||||
| -rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 8 |
4 files changed, 25 insertions, 29 deletions
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index e88f4f944f..7a4ee2674d 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -24,11 +24,6 @@ #include "SB800.h" #include <stdlib.h> -/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess? - * - * Board is known to have some issues with integrated NIC and - * might need implementation to drive some GPIOs. - */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); @@ -100,6 +95,9 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + /* this seems to be just copy-pasted from the AMD reference boards and needs + * some investigation + */ switch(MemData->ParameterListPtr->DDR3Voltage){ case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 00cdaa735c..2f2e58d751 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -24,7 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_WINBOND_W83627HF + select SUPERIO_NUVOTON_NCT5572D select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index e2096c07d4..0690664906 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -54,22 +54,15 @@ chip northbridge/amd/agesa/family14/root_complex end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end + device pci 14.3 on # LPC + chip superio/nuvoton/nct5572d + device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die + device pnp 2e.1 off end # LPT1; same as FDC device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off # IR io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -81,19 +74,24 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 2e.6 off # CIR io 0x60 = 0x100 + irq 0x70 = 0 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 + device pnp 2e.7 off end # GIPO689 + device pnp 2e.8 off end # WDT + device pnp 2e.9 off end # GPIO235 device pnp 2e.a on end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 + io 0x62 = 0x0000 # SB-TSI currently not implemented irq 0x70 = 5 end + device pnp 2e.c off end # PECI + device pnp 2e.d off end # SUSLED + device pnp 2e.e off # CIRWKUP + io 0x60 = 0x0000 + irq 0x70 = 0 + end + device pnp 2e.f off end # GPIO_PP_OD end end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 5223360686..47704ed269 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -33,14 +33,14 @@ #include "agesawrapper.h" #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5572d/nct5572d.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h" -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -61,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } |