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-rw-r--r--src/Kconfig4
-rw-r--r--src/arch/x86/include/arch/smp/spinlock.h7
-rw-r--r--src/cpu/amd/microcode/microcode.c19
3 files changed, 28 insertions, 2 deletions
diff --git a/src/Kconfig b/src/Kconfig
index a8b086913a..f6702eadaf 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -489,6 +489,10 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
SR565x, that cannot handle concurrent CBFS accesses from
multiple APs during early startup.
+config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
+ bool
+ default n
+
config HAVE_MONOTONIC_TIMER
def_bool n
help
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
index 057d9e3f8f..39a81d289c 100644
--- a/src/arch/x86/include/arch/smp/spinlock.h
+++ b/src/arch/x86/include/arch/smp/spinlock.h
@@ -1,7 +1,10 @@
#ifndef ARCH_SMP_SPINLOCK_H
#define ARCH_SMP_SPINLOCK_H
-#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)
+#if !defined(__PRE_RAM__) \
+ || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
+ || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
+ || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
/*
* Your basic SMP spinlocks, allowing only a single CPU anywhere
@@ -16,6 +19,8 @@ spinlock_t *romstage_console_lock(void);
void initialize_romstage_console_lock(void);
spinlock_t* romstage_nvram_cbfs_lock(void);
void initialize_romstage_nvram_cbfs_lock(void);
+spinlock_t* romstage_microcode_cbfs_lock(void);
+void initialize_romstage_microcode_cbfs_lock(void);
#endif
#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 37d395a560..314d07013b 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -20,6 +20,7 @@
#include <cpu/amd/microcode.h>
#include <cbfs.h>
#include <arch/io.h>
+#include <smp/spinlock.h>
#define UCODE_DEBUG(fmt, args...) \
do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0)
@@ -197,14 +198,30 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
return;
}
+#ifdef __PRE_RAM__
+#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+ spin_lock(romstage_microcode_cbfs_lock());
+#endif
+#endif
+
ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i],
CBFS_TYPE_MICROCODE, &ucode_len);
if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n");
-
+#ifdef __PRE_RAM__
+#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+ spin_unlock(romstage_microcode_cbfs_lock());
+#endif
+#endif
return;
}
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
+
+#ifdef __PRE_RAM__
+#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+ spin_unlock(romstage_microcode_cbfs_lock());
+#endif
+#endif
}
}