summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/mainboard/Kconfig3
-rw-r--r--src/mainboard/bifferos/Kconfig36
-rw-r--r--src/mainboard/bifferos/bifferboard/Kconfig19
-rw-r--r--src/mainboard/bifferos/bifferboard/Makefile.inc1
-rw-r--r--src/mainboard/bifferos/bifferboard/chip.h23
-rw-r--r--src/mainboard/bifferos/bifferboard/devicetree.cb8
-rw-r--r--src/mainboard/bifferos/bifferboard/mainboard.c26
-rw-r--r--src/mainboard/bifferos/bifferboard/romstage.c64
8 files changed, 180 insertions, 0 deletions
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index fe70211827..a968b51563 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -36,6 +36,8 @@ config VENDOR_AZZA
bool "AZZA"
config VENDOR_BCOM
bool "BCOM"
+config VENDOR_BIFFEROS
+ bool "Bifferos"
config VENDOR_BIOSTAR
bool "Biostar"
config VENDOR_BROADCOM
@@ -143,6 +145,7 @@ source "src/mainboard/avalue/Kconfig"
source "src/mainboard/axus/Kconfig"
source "src/mainboard/azza/Kconfig"
source "src/mainboard/bcom/Kconfig"
+source "src/mainboard/bifferos/Kconfig"
source "src/mainboard/biostar/Kconfig"
source "src/mainboard/broadcom/Kconfig"
source "src/mainboard/compaq/Kconfig"
diff --git a/src/mainboard/bifferos/Kconfig b/src/mainboard/bifferos/Kconfig
new file mode 100644
index 0000000000..98cbab8c71
--- /dev/null
+++ b/src/mainboard/bifferos/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if VENDOR_BIFFEROS
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_BIFFEROS_BIFFERBOARD
+ bool "Bifferboard"
+
+endchoice
+
+source "src/mainboard/bifferos/bifferboard/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Bifferos"
+
+endif # VENDOR_BIFFEROS
diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig
new file mode 100644
index 0000000000..4b4b5da263
--- /dev/null
+++ b/src/mainboard/bifferos/bifferboard/Kconfig
@@ -0,0 +1,19 @@
+if BOARD_BIFFEROS_BIFFERBOARD
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select ROMCC
+ select BOARD_ROMSIZE_KB_128
+ select NORTHBRIDGE_RDC_R8610
+ select SOUTHBRIDGE_RDC_R8610
+
+config MAINBOARD_DIR
+ string
+ default bifferos/bifferboard
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Bifferos"
+
+endif # BOARD_BIFFEROS_BIFFERBOARD
diff --git a/src/mainboard/bifferos/bifferboard/Makefile.inc b/src/mainboard/bifferos/bifferboard/Makefile.inc
new file mode 100644
index 0000000000..76784015ba
--- /dev/null
+++ b/src/mainboard/bifferos/bifferboard/Makefile.inc
@@ -0,0 +1 @@
+ROMCCFLAGS := -mcpu=i386 -O
diff --git a/src/mainboard/bifferos/bifferboard/chip.h b/src/mainboard/bifferos/bifferboard/chip.h
new file mode 100644
index 0000000000..be427834df
--- /dev/null
+++ b/src/mainboard/bifferos/bifferboard/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
+
diff --git a/src/mainboard/bifferos/bifferboard/devicetree.cb b/src/mainboard/bifferos/bifferboard/devicetree.cb
new file mode 100644
index 0000000000..757ddd52c9
--- /dev/null
+++ b/src/mainboard/bifferos/bifferboard/devicetree.cb
@@ -0,0 +1,8 @@
+chip northbridge/rdc/r8610
+ device pci_domain 0 on
+ device pci 0.0 on end
+ chip southbridge/rdc/r8610 # Southbridge
+ device pci 7.0 on end # SB
+ end
+ end
+end
diff --git a/src/mainboard/bifferos/bifferboard/mainboard.c b/src/mainboard/bifferos/bifferboard/mainboard.c
new file mode 100644
index 0000000000..5840f9519c
--- /dev/null
+++ b/src/mainboard/bifferos/bifferboard/mainboard.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Bifferos Bifferboard")
+};
+
diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c
new file mode 100644
index 0000000000..854aaa9ac4
--- /dev/null
+++ b/src/mainboard/bifferos/bifferboard/romstage.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+
+static void main(void)
+{
+ uint32_t tmp;
+ post_code(0x05);
+
+ /* Set timer1 to pulse generator 15us for memory refresh */
+ outb(0x54, 0x43);
+ outb(0x12, 0x41);
+
+ /* CPU setup, romcc pukes on invd() */
+ asm volatile ("invd");
+ enable_cache();
+
+ /* Set serial base */
+ pci_write_config32(PCI_DEV(0,7,0), 0x54, 0x3f8);
+ /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
+ pci_write_config32(PCI_DEV(0,7,0), 0x50, 0x84101012);
+
+ console_init();
+
+ /* memory init */
+ pci_write_config32(PCI_DEV(0,0,0), 0x68, 0x6c99f);
+ pci_write_config32(PCI_DEV(0,0,0), 0x6c, 0x800451);
+ pci_write_config32(PCI_DEV(0,0,0), 0x70, 0x4000003);
+
+ /* memory phase/buffer strength for read and writes */
+ tmp = pci_read_config32(PCI_DEV(0,0,0), 0x64);
+ tmp &= 0x0FF00FFFF;
+ tmp |= 0x790000;
+ pci_write_config32(PCI_DEV(0,0,0), 0x64, tmp);
+ /* Route Cseg, Dseg, Eseg and Fseg to RAM */
+ pci_write_config32(PCI_DEV(0,0,0), 0x84, 0x3ffffff0);
+}
+