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-rw-r--r--src/arch/riscv/virtual_memory.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index bea552de86..98b7edca4e 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -208,4 +208,14 @@ void mstatus_init(void)
clear_csr(mip, MIP_MSIP);
set_csr(mie, MIP_MSIP);
+
+ /* Configure which exception causes are delegated to supervisor mode */
+ set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH)
+ | (1 << CAUSE_FAULT_FETCH)
+ | (1 << CAUSE_ILLEGAL_INSTRUCTION)
+ | (1 << CAUSE_BREAKPOINT)
+ | (1 << CAUSE_FAULT_LOAD)
+ | (1 << CAUSE_FAULT_STORE)
+ | (1 << CAUSE_USER_ECALL)
+ );
}