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-rw-r--r--src/northbridge/intel/pineview/raminit.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 3413cc16e8..ee19b61841 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -2032,9 +2032,9 @@ static void sdram_mmap_regs(struct sysinfo *s)
gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];
tom = s->channel_capacity[0];
- /* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
- which requires to have TSEG_BASE aligned to TSEG_SIZE. */
- tsegsize = 0x2;
+ /* with GTT always being 1M, TSEG 1M is the only setting that can
+ be covered by SMRR which has alignment requirements. */
+ tsegsize = 0x1;
mmiosize = 0x400; // 1GB
reclaim = false;
@@ -2071,7 +2071,7 @@ static void sdram_mmap_regs(struct sysinfo *s)
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
reg8 &= ~0x7;
- reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
+ reg8 |= (0 << 1) | (1 << 0); /* 1M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);
printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",