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-rw-r--r--src/cpu/intel/haswell/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/socket_rPGA988B/Kconfig4
-rw-r--r--src/cpu/intel/socket_rPGA989/Kconfig4
-rw-r--r--src/northbridge/intel/haswell/Kconfig1
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig4
-rw-r--r--src/soc/intel/broadwell/Kconfig1
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc4
8 files changed, 0 insertions, 26 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 0a070b2e81..0978bfb0ac 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -151,7 +151,6 @@ clear_mtrrs:
wrmsr
post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
/* Enable caching for ram init code to run faster */
movl $MTRRphysBase_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -161,7 +160,6 @@ clear_mtrrs:
movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
-#endif
post_code(0x28)
/* Enable cache. */
@@ -219,7 +217,6 @@ before_romstage:
andl $~1, %eax
wrmsr
-#if CONFIG_CACHE_MRC_BIN
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
@@ -227,7 +224,6 @@ before_romstage:
wrmsr
movl $MTRRphysMask_MSR(2), %ecx
wrmsr
-#endif
post_code(0x33)
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 2d469ffa03..a3f1c649c1 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -146,7 +146,6 @@ clear_mtrrs:
wrmsr
post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
/* Enable caching for ram init code to run faster */
movl $MTRRphysBase_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -156,7 +155,6 @@ clear_mtrrs:
movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
-#endif
post_code(0x28)
/* Enable cache. */
@@ -211,7 +209,6 @@ before_romstage:
andl $~1, %eax
wrmsr
-#if CONFIG_CACHE_MRC_BIN
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
@@ -219,7 +216,6 @@ before_romstage:
wrmsr
movl $MTRRphysMask_MSR(2), %ecx
wrmsr
-#endif
post_code(0x33)
diff --git a/src/cpu/intel/socket_rPGA988B/Kconfig b/src/cpu/intel/socket_rPGA988B/Kconfig
index 471e5220cf..753cfb30c9 100644
--- a/src/cpu/intel/socket_rPGA988B/Kconfig
+++ b/src/cpu/intel/socket_rPGA988B/Kconfig
@@ -8,8 +8,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select MMX
select SSE
-config CACHE_MRC_BIN
- bool
- default n
-
endif
diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig
index 83d29e7d23..1d1f64fdbd 100644
--- a/src/cpu/intel/socket_rPGA989/Kconfig
+++ b/src/cpu/intel/socket_rPGA989/Kconfig
@@ -8,8 +8,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select MMX
select SSE
-config CACHE_MRC_BIN
- bool
- default n
-
endif
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 0a251b8a99..37dbd2b8da 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -19,7 +19,6 @@
config NORTHBRIDGE_INTEL_HASWELL
bool
- select CACHE_MRC_BIN
select CPU_INTEL_HASWELL
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 4dede09707..093224f841 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -19,7 +19,6 @@
config NORTHBRIDGE_INTEL_SANDYBRIDGE
bool
- select CACHE_MRC_BIN
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_206AX
@@ -27,7 +26,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
bool
- select CACHE_MRC_BIN
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_206AX
@@ -36,7 +34,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
- select CACHE_MRC_BIN
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_306AX
@@ -44,7 +41,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
bool
- select CACHE_MRC_BIN
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_306AX
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5853118268..524366c56f 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS
select VGA_ROM_RUN if !PAYLOAD_SEABIOS
select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS
select BACKUP_DEFAULT_SMM_REGION
- select CACHE_MRC_BIN
select CACHE_MRC_SETTINGS
select MRC_SETTINGS_PROTECT
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 05d4889f3f..3f1b12af18 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -153,7 +153,6 @@ clear_mtrrs:
wrmsr
post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
/* Enable caching for ram init code to run faster */
movl $MTRRphysBase_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -163,7 +162,6 @@ clear_mtrrs:
movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
-#endif
post_code(0x28)
/* Enable cache. */
@@ -239,7 +237,6 @@ before_romstage:
andl $~1, %eax
wrmsr
-#if CONFIG_CACHE_MRC_BIN
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
@@ -247,7 +244,6 @@ before_romstage:
wrmsr
movl $MTRRphysMask_MSR(2), %ecx
wrmsr
-#endif
post_code(0x33)