diff options
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b74291ebb3..d4d76cdb61 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -194,6 +194,7 @@ struct soc_intel_cannonlake_config { /* Heci related */ uint8_t Heci3Enabled; + uint8_t DisableHeciRetry; /* Gfx related */ uint8_t IgdDvmt50PreAlloc; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 010d152c76..7af90a73ed 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -128,6 +128,10 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) config->sata_port[i].TxGen3DeEmph; } } +#if !CONFIG(SOC_INTEL_COMETLAKE) + if (config->DisableHeciRetry) + tconfig->DisableHeciRetry = config->DisableHeciRetry; +#endif } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |