diff options
| -rw-r--r-- | src/mainboard/google/cyan/variants/reks/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/cyan/variants/reks/ramstage.c | 40 |
2 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index db2eea3d29..da5b5cc153 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -18,6 +18,7 @@ romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c +ramstage-y += ramstage.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/cyan/variants/reks/ramstage.c b/src/mainboard/google/cyan/variants/reks/ramstage.c new file mode 100644 index 0000000000..27f9dfa241 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/ramstage.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> + +void board_silicon_USB2_override(SILICON_INIT_UPD *params) +{ + if (SocStepping() >= SocD0) { + //D-Stepping + //USB2[1] right external port + params->Usb2Port1PerPortPeTxiSet = 7; + params->Usb2Port1PerPortTxiSet = 3; + params->Usb2Port1IUsbTxEmphasisEn = 2; + params->Usb2Port1PerPortTxPeHalf = 1; + + //USB2[2] left external port + params->Usb2Port2PerPortPeTxiSet = 7; + params->Usb2Port2PerPortTxiSet = 0; + params->Usb2Port2IUsbTxEmphasisEn = 2; + params->Usb2Port2PerPortTxPeHalf = 1; + + //USB2[3] CCD + params->Usb2Port3PerPortPeTxiSet = 7; + params->Usb2Port3PerPortTxiSet = 0; + params->Usb2Port3IUsbTxEmphasisEn = 2; + params->Usb2Port3PerPortTxPeHalf = 1; + } +} |