diff options
| -rw-r--r-- | src/mainboard/roda/rk9/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/roda/rk9/gpio.c | 140 | ||||
| -rw-r--r-- | src/mainboard/roda/rk9/romstage.c | 29 |
3 files changed, 144 insertions, 27 deletions
diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index f92382ee43..7ff15887ca 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +romstage-y = gpio.c + ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c ramstage-y += cstates.c ramstage-y += blc.c diff --git a/src/mainboard/roda/rk9/gpio.c b/src/mainboard/roda/rk9/gpio.c new file mode 100644 index 0000000000..4e1ebe3cda --- /dev/null +++ b/src/mainboard/roda/rk9/gpio.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index b88671c705..ff8bc874c5 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <romstage_handoff.h> #include <console/console.h> +#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> #include <superio/smsc/lpc47n227/lpc47n227.h> @@ -34,32 +35,6 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) -static void default_southbridge_gpio_setup(void) -{ - /* Enable GPIOs [31:0]. */ - outl(0x197e7dfe, DEFAULT_GPIOBASE + 0x00); - /* Set input/output mode [31:0] (0 == out, 1 == in). */ - outl(0xe0ea43fe, DEFAULT_GPIOBASE + 0x04); - /* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT, - WLAN, ~ANTMUX, ~GPIO12, - ~SUSPWR, SMBALERT) */ - outl(0x00000800, DEFAULT_GPIOBASE + 0x0c); - - /* Disable blink [31:0]. */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); - /* Set input inversion [31:0]. */ - outl(0x00000182, DEFAULT_GPIOBASE + 0x2c); - - /* Enable GPIOs [60:32]. */ - outl(0x130300fe, DEFAULT_GPIOBASE + 0x30); - /* Set input/output mode [60:32] (0 == out, 1 == in). */ - outl(0x0e55ffb0, DEFAULT_GPIOBASE + 0x34); - /* Set gpio levels [60:32]. orig: 0x10020046 (LNKALERT, ~ATAIO, - DMITERM, TXT, ~CLKSATA, - GPS, AUDIO) */ - outl(0x10020042, DEFAULT_GPIOBASE + 0x38); -} - static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -142,7 +117,7 @@ void mainboard_romstage_entry(unsigned long bist) gm45_early_reset(); } - default_southbridge_gpio_setup(); + setup_pch_gpios(&mainboard_gpio_map); /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); |