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-rw-r--r--src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl80
-rw-r--r--src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl80
-rw-r--r--src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl80
-rw-r--r--src/northbridge/intel/gm45/acpi/hostbridge.asl3
-rw-r--r--src/northbridge/intel/gm45/northbridge.c17
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig1
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c9
7 files changed, 27 insertions, 243 deletions
diff --git a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl
deleted file mode 100644
index aefdf944eb..0000000000
--- a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * gm45
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Onboard GbE
- Package() { 0x0019ffff, 0, 0, 16 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, 0, 16 },
- Package() { 0x001affff, 1, 0, 17 },
- Package() { 0x001affff, 2, 0, 18 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 17 },
- Package() { 0x001dffff, 2, 0, 18 },
- // LPC bridge sub devices 0:1f.x
- Package() { 0x001fffff, 1, 0, 17 },
- Package() { 0x001fffff, 2, 0, 18 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard GbE
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // LPC bridge sub devices 0:1f.x
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
- })
- }
-}
diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
deleted file mode 100644
index aefdf944eb..0000000000
--- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * gm45
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Onboard GbE
- Package() { 0x0019ffff, 0, 0, 16 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, 0, 16 },
- Package() { 0x001affff, 1, 0, 17 },
- Package() { 0x001affff, 2, 0, 18 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 17 },
- Package() { 0x001dffff, 2, 0, 18 },
- // LPC bridge sub devices 0:1f.x
- Package() { 0x001fffff, 1, 0, 17 },
- Package() { 0x001fffff, 2, 0, 18 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard GbE
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // LPC bridge sub devices 0:1f.x
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
- })
- }
-}
diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl
deleted file mode 100644
index 4a9ede8e72..0000000000
--- a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * gm45
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, 0, 16 },
- Package() { 0x001affff, 1, 0, 17 },
- Package() { 0x001affff, 2, 0, 18 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 17 },
- Package() { 0x001dffff, 2, 0, 18 },
- // FIXME
- // CardBus/IEEE1394 0:1e.2, 0:1e.3
- // Package() { 0x001effff, 0, 0, 22 },
- // Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 16 },
- Package() { 0x001fffff, 1, 0, 17 },
- Package() { 0x001fffff, 2, 0, 18 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // USB and EHCI 0:1a.x
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- // FIXME
- // CardBus/IEEE1394 0:1e.2, 0:1e.3
- // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
- })
- }
-}
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl
index c674df50d5..afa7a61404 100644
--- a/src/northbridge/intel/gm45/acpi/hostbridge.asl
+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl
@@ -228,6 +228,3 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/gm45_pci_irqs.asl"
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 4c42513bd0..663a9ff579 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -191,6 +191,22 @@ static void mch_domain_init(struct device *dev)
pci_write_config32(dev, PCI_COMMAND, reg32);
}
+static const char *northbridge_acpi_name(const struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
+ return NULL;
+
+ switch (dev->path.pci.devfn) {
+ case PCI_DEVFN(0, 0):
+ return "MCHC";
+ }
+
+ return NULL;
+}
+
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,
.set_resources = mch_domain_set_resources,
@@ -199,6 +215,7 @@ static struct device_operations pci_domain_ops = {
.scan_bus = pci_domain_scan_bus,
.write_acpi_tables = northbridge_write_acpi_tables,
.acpi_fill_ssdt_generator = generate_cpu_entries,
+ .acpi_name = northbridge_acpi_name,
};
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index fcf2eb5275..a6debcc378 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -18,6 +18,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
bool
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select IOAPIC
select HAVE_USBDEBUG
select HAVE_HARD_RESET
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 76f16e7853..18bfcf37a6 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -34,6 +34,7 @@
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
#include <drivers/intel/gma/i915.h>
+#include <southbridge/intel/common/acpi_pirq_gen.h>
#define NMI_OFF 0
@@ -558,12 +559,19 @@ static void southbridge_inject_dsdt(struct device *dev)
}
}
+
+static const char *lpc_acpi_name(const struct device *dev)
+{
+ return "LPCB";
+}
+
static void southbridge_fill_ssdt(struct device *device)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
+ intel_acpi_gen_def_acpi_pirq(device);
}
static struct pci_operations pci_ops = {
@@ -577,6 +585,7 @@ static struct device_operations device_ops = {
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.write_acpi_tables = acpi_write_hpet,
.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
+ .acpi_name = lpc_acpi_name,
.init = lpc_init,
.scan_bus = scan_lpc_bus,
.ops_pci = &pci_ops,
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 21:41:46 +0000