summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/cpu/intel/haswell/cache_as_ram.inc8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index fe595fbd22..9cdb176ea4 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -209,14 +209,6 @@ before_romstage:
andl $~1, %eax
wrmsr
- /* Clear MTRR that was used to cache MRC */
- xorl %eax, %eax
- xorl %edx, %edx
- movl $MTRR_PHYS_BASE(2), %ecx
- wrmsr
- movl $MTRR_PHYS_MASK(2), %ecx
- wrmsr
-
post_code(0x33)
/* Enable cache. */