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-rw-r--r--src/mainboard/google/hatch/variants/dratini/overridetree.cb9
-rw-r--r--src/mainboard/google/hatch/variants/jinlon/overridetree.cb9
2 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
index f820629198..5c30a5a93f 100644
--- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
@@ -17,6 +17,15 @@ chip soc/intel/cannonlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
+ # VR Slew rate setting
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "FastPkgCRampDisableIa" = "1"
+ register "FastPkgCRampDisableGt" = "1"
+ register "FastPkgCRampDisableSa" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index c9613d2677..f3f6c3b949 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -17,6 +17,15 @@ chip soc/intel/cannonlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
+ # VR Slew rate setting
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "FastPkgCRampDisableIa" = "1"
+ register "FastPkgCRampDisableGt" = "1"
+ register "FastPkgCRampDisableSa" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |