diff options
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index f78fe2c3ee..cade987313 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -40,6 +40,16 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" register "gen4_dec" = "0x000c0081" + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + register "PrmrrSize" = "0" # Enable PCH PCIE RP 5 using CLK 2 |