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-rw-r--r--src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl
index 3d31502526..f9f48bf04a 100644
--- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl
+++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl
@@ -11,8 +11,7 @@ Scope (\_SB.PCI0) {
/* IsCLK PCH base register for clock settings */
Name (ICKB, 0)
- Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB)
-
+ ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1
/*
* Arg0 : Clock Number
* Return : Offset of register to control the clock in Arg0