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-rw-r--r--src/soc/intel/cannonlake/acpi/ish.asl22
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl3
2 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/ish.asl b/src/soc/intel/cannonlake/acpi/ish.asl
new file mode 100644
index 0000000000..1c832b4ea9
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/ish.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:13.0 */
+
+Device (ISHB)
+{
+ Name (_ADR, 0x00130000)
+ Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index dfa29751a6..ae8de6a1df 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -51,6 +51,9 @@
/* SMBus 0:1f.4 */
#include "smbus.asl"
+/* ISH 0:13.0 */
+#include "ish.asl"
+
/* USB XHCI 0:14.0 */
#include "xhci.asl"