diff options
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/p2sb.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h new file mode 100644 index 0000000000..b90bc73cc1 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <commonlib/helpers.h> + +/* + * Currently all known xeon-sp CPUs use C620 PCH. These definitions + * come from C620 datasheet (Intel Doc #336067-007US) + */ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) +#define PCH_P2SB_EPMASK0 0xb0 +#define P2SB_SIZE (16 * MiB) |