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-rw-r--r--src/mainboard/sapphire/Kconfig16
-rw-r--r--src/mainboard/sapphire/Kconfig.name2
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/Kconfig68
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/Kconfig.name2
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/Makefile.inc19
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl0
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl30
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl0
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/acpi_tables.c34
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/board_info.txt6
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/cmos.default8
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/cmos.layout125
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/devicetree.cb166
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/dsdt.asl46
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/gma-mainboard.ads21
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/gpio.c189
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/hda_verb.c87
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/mainboard.c39
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/romstage.c90
19 files changed, 948 insertions, 0 deletions
diff --git a/src/mainboard/sapphire/Kconfig b/src/mainboard/sapphire/Kconfig
new file mode 100644
index 0000000000..130c1f4f22
--- /dev/null
+++ b/src/mainboard/sapphire/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_SAPPHIRE
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/sapphire/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/sapphire/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Sapphire"
+
+endif # VENDOR_SAPPHIRE
diff --git a/src/mainboard/sapphire/Kconfig.name b/src/mainboard/sapphire/Kconfig.name
new file mode 100644
index 0000000000..8ea84ad939
--- /dev/null
+++ b/src/mainboard/sapphire/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_SAPPHIRE
+ bool "Sapphire"
diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig
new file mode 100644
index 0000000000..c01a524363
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig
@@ -0,0 +1,68 @@
+if BOARD_SAPPHIRE_PUREPLATINUMH61
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA1155
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select USE_NATIVE_RAMINIT
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SUPERIO_FINTEK_F71808A
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_ACPI_RESUME
+ select MAINBOARD_HAS_LIBGFXINIT
+ select INTEL_INT15
+ select UDELAY_TSC
+ select SERIRQ_CONTINUOUS_MODE
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default sapphire/pureplatinumh61
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Pure Platinum H61"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0162.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0162"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x1007
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x174b
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX #USB port on the back under the Bluetooth module
+ int
+ default 4
+endif
diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig.name b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name
new file mode 100644
index 0000000000..7b642bd5ac
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SAPPHIRE_PUREPLATINUMH61
+ bool "Pure Platinum H61"
diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc
new file mode 100644
index 0000000000..7c555f9c32
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc
@@ -0,0 +1,19 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl
new file mode 100644
index 0000000000..86af6f437c
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
new file mode 100644
index 0000000000..a790b0bea5
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/sapphire/pureplatinumh61/board_info.txt b/src/mainboard/sapphire/pureplatinumh61/board_info.txt
new file mode 100644
index 0000000000..c6360e2256
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/board_info.txt
@@ -0,0 +1,6 @@
+Category: mini
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: n
+Release year: 2011
diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.default b/src/mainboard/sapphire/pureplatinumh61/cmos.default
new file mode 100644
index 0000000000..767372cd23
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/cmos.default
@@ -0,0 +1,8 @@
+boot_option=Fallback
+baud_rate=115200
+debug_level=Spew
+power_on_after_fail=Enable
+nmi=Enable
+volume=0x3
+sata_mode=AHCI
+hyper_threading=Enable
diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.layout b/src/mainboard/sapphire/pureplatinumh61/cmos.layout
new file mode 100644
index 0000000000..a90e27dc51
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/cmos.layout
@@ -0,0 +1,125 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+400 8 h 0 volume
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+#411 10 r 0 unused
+421 1 e 9 sata_mode
+#422 2 r 0 unused
+
+# coreboot config options: cpu
+424 1 e 2 hyper_threading
+#425 7 r 0 unused
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+#435 549 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 IDE
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
new file mode 100644
index 0000000000..a44e19d700
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -0,0 +1,166 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/sandybridge
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "0"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "0"
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_dp_b_hotplug" = "0"
+ register "gpu_dp_c_hotplug" = "0"
+ register "gpu_dp_d_hotplug" = "0"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "0"
+ register "gpu_panel_power_backlight_on_delay" = "0"
+ register "gpu_panel_power_cycle_delay" = "0"
+ register "gpu_panel_power_down_delay" = "0"
+ register "gpu_panel_power_up_delay" = "0"
+ register "gpu_pch_backlight" = "0x00000000"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_LGA1155
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x000c0291"
+ register "gen2_dec" = "0x000c0a01"
+ register "gen3_dec" = "0x00000000"
+ register "gen4_dec" = "0x00000000"
+ register "p_cnt_throttling_supported" = "0"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x174b 0x1007
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x8086 0x1c20
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1c.1 off # PCIe Port #2
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 on # PCIe Port #5
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1c.5 on # PCIe Port #6
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x174b 0x1007
+ chip superio/fintek/f71808a
+ register "multi_function_register_0" = "0x00"
+ register "multi_function_register_1" = "0xc4"
+ register "multi_function_register_2" = "0x21"
+ register "multi_function_register_3" = "0x2f"
+ register "multi_function_register_4" = "0x5c"
+ register "hwm_peci_tsi_ctrl" = "0x02" # PECI enabled, 1.23 V
+ register "hwm_tcc_temp" = "0x66" # TCC temperature = 102 °C
+ register "hwm_fan1_seg1_speed" = "0xff" # Fan 1 segment 1 = 100%
+ register "hwm_fan1_seg2_speed" = "0xdb" # Fan 1 segment 2 = 86%
+ register "hwm_fan1_seg3_speed" = "0xbc" # Fan 1 segment 3 = 74%
+ register "hwm_fan1_seg4_speed" = "0x9e" # Fan 1 segment 4 = 62%
+ register "hwm_fan1_seg5_speed" = "0x7f" # Fan 1 segment 5 = 50%
+ register "hwm_fan1_temp_src" = "0x18" # Fan 1 source = PECI
+ register "hwm_fan2_seg1_speed" = "0xff" # Fan 2 segment 1 = 100%
+ register "hwm_fan2_seg2_speed" = "0xdb" # Fan 2 segment 2 = 86%
+ register "hwm_fan2_seg3_speed" = "0xbc" # Fan 2 segment 3 = 74%
+ register "hwm_fan2_seg4_speed" = "0x9e" # Fan 2 segment 4 = 62%
+ register "hwm_fan2_seg5_speed" = "0x7f" # Fan 2 segment 5 = 50%
+ register "hwm_fan2_temp_src" = "0x1e" # Fan 2 source = temperature 2
+ device pnp 4e.1 off end # Serial Port 1
+ device pnp 4e.4 on # Hardware monitor
+ io 0x60 = 0x295
+ irq 0x70 = 0
+ end
+ device pnp 4e.5 off end # Keyboard
+ device pnp 4e.6 on # GPIO
+ irq 0xc5 = 0x1f
+ end
+ device pnp 4e.7 on # WDT
+ io 0x60 = 0xa00
+ end
+ device pnp 4e.8 off end # CIR
+ device pnp 4e.a off # PME, ACPI, EUP
+ irq 0xf8 = 0x00
+ irq 0xf9 = 0x09
+ irq 0xfa = 0x00
+ end
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x174b 0x1007
+ end
+ device pci 01.0 on # PCIe Bridge for discrete graphics
+ subsystemid 0x174b 0x1007
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x8086 0x2010
+ end
+ end
+end
diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl
new file mode 100644
index 0000000000..eb98bb29bc
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+ }
+ }
+}
diff --git a/src/mainboard/sapphire/pureplatinumh61/gma-mainboard.ads b/src/mainboard/sapphire/pureplatinumh61/gma-mainboard.ads
new file mode 100644
index 0000000000..cf866174d8
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/gma-mainboard.ads
@@ -0,0 +1,21 @@
+with HW.GFX.GMA;
+
+use HW.GFX.GMA;
+
+private package GMA.Mainboard is
+
+ -- For a three-pipe setup, bandwidth is shared between the 2nd and
+ -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely
+ -- have a high-resolution display attached first, `Internal` last.
+
+ ports : constant Port_List :=
+ (DP2,
+ DP3,
+ Digital1,
+ Digital2,
+ Digital3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c
new file mode 100644
index 0000000000..5dbb223bfc
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c
@@ -0,0 +1,189 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio6 = GPIO_DIR_OUTPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio6 = GPIO_LEVEL_LOW,
+ .gpio9 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_LOW,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+ .gpio6 = GPIO_NO_BLINK,
+ .gpio9 = GPIO_NO_BLINK,
+ .gpio15 = GPIO_NO_BLINK,
+ .gpio22 = GPIO_NO_BLINK,
+ .gpio24 = GPIO_NO_BLINK,
+ .gpio25 = GPIO_NO_BLINK,
+ .gpio26 = GPIO_NO_BLINK,
+ .gpio27 = GPIO_NO_BLINK,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio10 = GPIO_NO_INVERT,
+ .gpio12 = GPIO_NO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_NO_INVERT,
+ .gpio28 = GPIO_NO_INVERT,
+ .gpio29 = GPIO_NO_INVERT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio6 = GPIO_RESET_PWROK,
+ .gpio7 = GPIO_RESET_PWROK,
+ .gpio8 = GPIO_RESET_PWROK,
+ .gpio9 = GPIO_RESET_PWROK,
+ .gpio10 = GPIO_RESET_PWROK,
+ .gpio12 = GPIO_RESET_PWROK,
+ .gpio13 = GPIO_RESET_PWROK,
+ .gpio14 = GPIO_RESET_PWROK,
+ .gpio15 = GPIO_RESET_PWROK,
+ .gpio22 = GPIO_RESET_PWROK,
+ .gpio23 = GPIO_RESET_PWROK,
+ .gpio24 = GPIO_RESET_PWROK,
+ .gpio25 = GPIO_RESET_PWROK,
+ .gpio26 = GPIO_RESET_PWROK,
+ .gpio27 = GPIO_RESET_PWROK,
+ .gpio28 = GPIO_RESET_PWROK,
+ .gpio29 = GPIO_RESET_PWROK,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_OUTPUT,
+ .gpio39 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_LOW,
+ .gpio39 = GPIO_LEVEL_LOW,
+ .gpio48 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_reset = {
+ .gpio35 = GPIO_RESET_PWROK,
+ .gpio37 = GPIO_RESET_PWROK,
+ .gpio38 = GPIO_RESET_PWROK,
+ .gpio39 = GPIO_RESET_PWROK,
+ .gpio48 = GPIO_RESET_PWROK,
+ .gpio60 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_reset = {
+ .gpio68 = GPIO_RESET_PWROK,
+ .gpio69 = GPIO_RESET_PWROK,
+ .gpio72 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c
new file mode 100644
index 0000000000..cf723d0867
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */
+ 0x10ec0000, /* Subsystem ID */
+
+ 0x0000000f, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x2, 0x10ec0000),
+
+ /* NID 0x11. */
+ AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0),
+
+ /* NID 0x14. */
+ AZALIA_PIN_CFG(0x2, 0x14, 0x01014c10),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x2, 0x15, 0x01011c12),
+
+ /* NID 0x16. */
+ AZALIA_PIN_CFG(0x2, 0x16, 0x01016c11),
+
+ /* NID 0x17. */
+ AZALIA_PIN_CFG(0x2, 0x17, 0x01012c14),
+
+ /* NID 0x18. */
+ AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c40),
+
+ /* NID 0x19. */
+ AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c50),
+
+ /* NID 0x1a. */
+ AZALIA_PIN_CFG(0x2, 0x1a, 0x01813c4f),
+
+ /* NID 0x1b. */
+ AZALIA_PIN_CFG(0x2, 0x1b, 0x0321403f),
+
+ /* NID 0x1c. */
+ AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0),
+
+ /* NID 0x1d. */
+ AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601),
+
+ /* NID 0x1e. */
+ AZALIA_PIN_CFG(0x2, 0x1e, 0x0145e130),
+
+ /* NID 0x1f. */
+ AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0),
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c
new file mode 100644
index 0000000000..926031da5b
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_init(device_t dev)
+{
+ RCBA32(0x38c8) = 0x00002009;
+ RCBA32(0x38c4) = 0x00802009;
+ RCBA32(0x38c0) = 0x00000007;
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
new file mode 100644
index 0000000000..be692f6b98
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <southbridge/intel/common/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <delay.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
+}
+
+void rcba_config(void)
+{
+ /* Disable devices. */
+ RCBA32(0x3414) = 0x00000020;
+ RCBA32(0x3418) = 0x1fce1fe3;
+
+}
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+ if (s3resume) {
+ /*
+ * Raminit after S3 resume fails if started too early; a delay
+ * of 10 ms seems to be sufficient to fix the issue.
+ */
+ mdelay(10);
+ }
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x51, id_only);
+}