diff options
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/Config.lb | 284 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/Options.lb | 311 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/acpi_tables.c | 295 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/auto.c | 364 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/chip.h | 25 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/cmos.layout | 134 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/debug.c | 128 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/dmi.h | 31 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/dsdt.dsl | 303 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/fadt.c | 86 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/irq_tables.c | 63 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/mainboard.c | 29 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/mptable.c | 131 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/power_reset_check.c | 31 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/reset.c | 33 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/rtl8168.c | 49 | ||||
| -rw-r--r-- | targets/kontron/986lcd-m/Config-abuild.lb | 30 | ||||
| -rw-r--r-- | targets/kontron/986lcd-m/Config.lb | 22 |
18 files changed, 2349 insertions, 0 deletions
diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb new file mode 100644 index 0000000000..4ba6eac758 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/Config.lb @@ -0,0 +1,284 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=(64*1024) +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +driver rtl8168.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end + +if HAVE_ACPI_TABLES + object fadt.o + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv $(PWD)/dsdt.hex dsdt.c" + end + object ./dsdt.o +end + +object reset.o + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end + +## +## Build our 16 bit and 32 bit coreboot entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + ldscript /cpu/x86/car/cache_as_ram.lds +end + +## +## Build our reset vector (This is where coreboot is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +## +## Setup Cache-As-Ram +## +mainboardinit cpu/intel/model_6ex/cache_as_ram.inc + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +end + +### +### O.k. We aren't just an intermediary anymore! +### + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/i945 + + device apic_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device apic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 01.0 off end # i945 PCIe root port + chip drivers/pci/onboard + device pci 02.0 on end # vga controller + register "rom_address" = "0xfff00000" + end + device pci 02.1 on end # display controller + + chip southbridge/intel/i82801gx + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x1" + register "sata_ahci" = "0x0" + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627thg + device pnp 2e.0 off # Floppy + end + device pnp 2e.1 off # Parport + end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + end + device pnp 2e.5 on # Keyboard+Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + irq 0xf0 = 0x82 # HW accel A20. + end + device pnp 2e.7 on # GPIO1, GAME, MIDI + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 2e.8 on # GPIO2 + # all default + end + device pnp 2e.9 on # GPIO3/4 + irq 0x30 = 0x03 # does this work? + irq 0xf0 = 0xfb # set inputs/outputs + irq 0xf1 = 0x66 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # HWM + io 0x60 = 0xa00 + irq 0x70 = 0 + end + + end + chip superio/winbond/w83627thg + device pnp 4e.0 off # Floppy + end + device pnp 4e.1 off # Parport + end + device pnp 4e.2 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 11 + end + device pnp 4e.3 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 10 + end + device pnp 4e.5 off # Keyboard + end + device pnp 4e.7 off # GPIO1, GAME, MIDI + end + device pnp 4e.8 off # GPIO2 + end + device pnp 4e.9 off # GPIO3/4 + end + device pnp 4e.a off # ACPI + end + device pnp 4e.b off # HWM + end + end + + end + #device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + #device pci 1f.4 off end # Realtek ID Codec + end + end +end diff --git a/src/mainboard/kontron/986lcd-m/Options.lb b/src/mainboard/kontron/986lcd-m/Options.lb new file mode 100644 index 0000000000..926e69820b --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/Options.lb @@ -0,0 +1,311 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +# Tables +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses HAVE_ACPI_TABLES +# SMP +uses CONFIG_SMP +uses CONFIG_LOGICAL_CPUS +uses CONFIG_AP_IN_SIPI_WAIT +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_IOAPIC +# Image Size +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +# Payload +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +# Build Internals +uses _RAMBASE +uses _ROMBASE +uses STACK_SIZE +uses HEAP_SIZE +uses CONFIG_CHIP_NAME +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses CONFIG_USE_INIT +uses CONFIG_USE_PRINTK_IN_CAR +uses XIP_ROM_BASE +uses XIP_ROM_SIZE +uses HAVE_HARD_RESET +uses HAVE_SMI_HANDLER +uses CONFIG_PCIE_CONFIGSPACE_HOLE +# +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +# Timers +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +# Console +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +# Toolchain +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY +# Tweaks +uses CONFIG_GDB_STUB +uses MAX_REBOOT_CNT +uses USE_WATCHDOG_ON_BOOT +uses COREBOOT_EXTRA_VERSION +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL + +### +### Build options +### + +## +## +default MAX_REBOOT_CNT=3 + +## +## Use the watchdog to break out of a lockup condition +## +default USE_WATCHDOG_ON_BOOT=0 + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=1024*1024 + + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from coreboot +## +default HAVE_HARD_RESET=1 + +## +## Build SMI handler +## +default HAVE_SMI_HANDLER=1 + +## +## Leave a hole for mmapped PCIe config space +## + +default CONFIG_PCIE_CONFIGSPACE_HOLE=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=18 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to provide ACPI support +## +default HAVE_ACPI_TABLES=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default coreboot cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_MAX_PHYSICAL_CPUS=2 +default CONFIG_LOGICAL_CPUS=1 +default CONFIG_AP_IN_SIPI_WAIT=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_SIZE=0x8000 +default DCACHE_RAM_BASE=( 0xfff00000 - DCACHE_RAM_SIZE - 1024*1024) +default CONFIG_USE_PRINTK_IN_CAR=1 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="986LCD-M" +default MAINBOARD_VENDOR= "KONTRON" + +### +### coreboot layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (coreboot plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## coreboot C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_PAYLOAD=1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=5 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=9 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## chip name +## +default CONFIG_CHIP_NAME=1 + + +### End Options.lb +end diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c new file mode 100644 index 0000000000..2e1b0b4346 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -0,0 +1,295 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "dmi.h" + +extern unsigned char AmlCode[]; + +typedef struct acpi_oemb { + acpi_header_t header; + u8 ss; + u16 iost; + u32 topm; + u32 roms; + u32 mg1b; + u32 mg1l; + u32 mg2b; + u32 mg2l; + u8 rsvd; + u8 dmax; + u32 hpta; + u32 cpb0; + u32 cpb1; + u32 cpb2; + u32 cpb3; + u8 assb; + u8 aotb; + u32 aaxb; + u8 smif; + u8 dtse; + u8 dts1; + u8 dts2; + u8 mpen; +} __attribute__((packed)) acpi_oemb_t; + +void acpi_create_oemb(acpi_oemb_t *oemb) +{ + acpi_header_t *header = &(oemb->header); + unsigned long tolud; + + memset (oemb, 0, sizeof(oemb)); + + /* fill out header fields */ + memcpy(header->signature, "OEMB", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_oemb_t); + header->revision = 1; + + oemb->ss = 0x09; // ss1 + ss 4 + oemb->iost = 0x0403; // ?? + + tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c); + oemb->topm = tolud; + + oemb->roms = 0xfff00000; // 1M hardcoded + + oemb->mg1b = 0x000d0000; + oemb->mg1l = 0x00010000; + + oemb->mg2b = tolud; + oemb->mg2l = 0-tolud; + + oemb->dmax = 0x87; + oemb->hpta = 0x000e36c0; + + header->checksum = + acpi_checksum((void *) oemb, sizeof(acpi_oemb_t)); + +}; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ +#if 0 + device_t dev; + u64 mmcfg; + + dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 + if (!dev) + return current; + + // MMCFG not supported or not enabled. + if ((pci_read_config8(dev, 0x40) & 0xC0) != 0xC0) + return current; + + mmcfg = ((u64) pci_read_config8(dev, 0x41)) << 28; + if (!mmcfg) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, mmcfg, 0x0, 0x0, 0xff); +#endif + return current; +} + +void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ +#define HPET_ADDR 0xfe800000ULL + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, HPET_NAME, 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + // XXX factory bios just puts an address here -- who's right? + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x80861234; /* VIA */ + hpet->number = 0x00; + hpet->min_tick = 0x0090; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + + + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local Apic */ + current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0); + // This one is for the second core... Will it hurt? + current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d); // high/level + + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_oemb_t *oemb; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16byte */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ +#if 0 + printk_debug("ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdt, hpet); +#endif + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdt, madt); +#if 0 + printk_debug("ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdt, mcfg); +#endif + + printk_debug("ACPI: * OEMB\n"); + oemb=(acpi_oemb_t *)current; + current += sizeof(acpi_oemb_t); + ALIGN_CURRENT; + acpi_create_oemb(oemb); + acpi_add_table(rsdt, oemb); + + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + current += ((acpi_header_t *) AmlCode)->length; + ALIGN_CURRENT; + memcpy((void *) dsdt, (void *) AmlCode, + ((acpi_header_t *) AmlCode)->length); + +#if 1 + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk_debug("ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb); + *(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb; + break; + } + } + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum(dsdt, dsdt->length); +#endif + + printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + dsdt->length); + + printk_debug("ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + printk_debug("current = %x\n", current); + + printk_debug("ACPI: * DMI (Linux workaround)\n"); + memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); + + printk_info("ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/kontron/986lcd-m/auto.c b/src/mainboard/kontron/986lcd-m/auto.c new file mode 100644 index 0000000000..c708f1ae15 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/auto.c @@ -0,0 +1,364 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __ROMCC__ means: use "unsigned" for device, not a struct. +#define __ROMCC__ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> + +#include "superio/winbond/w83627thg/w83627thg.h" + +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" + +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include <cpu/x86/bist.h> + +#include "ram/ramtest.c" +#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +#include "reset.c" +#include "superio/winbond/w83627thg/w83627thg_early_serial.c" + +#include "northbridge/intel/i945/udelay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +#include "northbridge/intel/i945/ich7.h" +static void setup_ich7_gpios(void) +{ + /* TODO: This is highly board specific and should be moved */ + printk_debug(" GPIOS..."); + /* General Registers */ + outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ +} + +#include "northbridge/intel/i945/early_init.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +/* Usually system firmware turns off system memory clock signals to + * unused SO-DIMM slots to reduce EMI and power consumption. + * However, the Kontron 986LCD-M does not like unused clock signals to + * be disabled. If other similar mainboard occur, it would make sense + * to make this an entry in the sysinfo structure, and pre-initialize that + * structure in the mainboard's auto.c main() function. For now a + * #define will do. + */ +#define OVERRIDE_CLOCK_DISABLE 1 +#include "northbridge/intel/i945/raminit.h" +#include "northbridge/intel/i945/raminit.c" +#include "northbridge/intel/i945/reset_test.c" +#include "northbridge/intel/i945/errata.c" +#include "debug.c" + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + // Enable HWM at 0xa00 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0a01); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); +} + + +/* This box has two superios, so enabling serial becomes slightly excessive. + * We disable a lot of stuff to make sure that there are no conflicts between + * the two. Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +static void early_superio_config_w83627thg(void) +{ + device_t dev; + + dev=PNP_DEV(0x2e, W83627THG_SP1); + pnp_enter_ext_func_mode(dev); + + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + // pnp_write_config(dev, 0xf1, 4); // IRMODE0 + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + // pnp_write_config(dev, 0xf0, 0x82); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_GPIO2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); // Just enable it + + dev=PNP_DEV(0x2e, W83627THG_GPIO3); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output + pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 + pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + + dev=PNP_DEV(0x2e, W83627THG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x2e, W83627THG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_exit_ext_func_mode(dev); + + dev=PNP_DEV(0x4e, W83627THG_SP1); + pnp_enter_ext_func_mode(dev); + + pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 11); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627THG_SP2); + pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 10); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627THG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x4e, W83627THG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x4e, W83627THG_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); + + pnp_exit_ext_func_mode(dev); +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + //RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x3241; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3210; + RCBA16(0x3148) = 0x3210; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable unused devices */ + RCBA32(0x3418) = 0x000e0063; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +#if USE_FALLBACK_IMAGE == 1 +#include "southbridge/intel/i82801gx/cmos_failover.c" +#endif + +void real_main(unsigned long bist) +{ + int boot_mode = 0; + + if (bist == 0) { + enable_lapic(); + } + + ich7_enable_lpc(); + early_superio_config_w83627thg(); + + /* Set up the console */ + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk_debug("soft reset detected.\n"); + boot_mode = 1; + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + sdram_initialize(boot_mode); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + +#if DEFAULT_CONSOLE_LOGLEVEL > 8 +#if defined(DEBUG_RAM_SETUP) + sdram_dump_mchbar_registers(); +#endif + + { + /* This will not work if TSEG is in place! */ + u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + + printk_debug("TOM: 0x%08x\n", tom); + ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, tom); + } +#endif + MCHBAR16(SSKPD) = 0xCAFE; +} + +#include "cpu/intel/model_6ex/cache_as_ram_disable.c" diff --git a/src/mainboard/kontron/986lcd-m/chip.h b/src/mainboard/kontron/986lcd-m/chip.h new file mode 100644 index 0000000000..abc9e8b0be --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/chip.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +struct chip_operations mainboard_kontron_986lcd_m_ops; +struct mainboard_kontron_986lcd_m_config { + int nothing; +}; diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout new file mode 100644 index 0000000000..ba42513c9c --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -0,0 +1,134 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 1 e 1 power_on_after_fail +#410 6 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 80 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/kontron/986lcd-m/debug.c b/src/mainboard/kontron/986lcd-m/debug.c new file mode 100644 index 0000000000..ecd6b7e2d1 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/debug.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x53 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff, + (dev >> 15) & 0x1f, (dev >> 12) & 7); + printk_debug(" [%04x:%04x]\r\n", id &0xffff, id >> 16); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + + printk_debug("PCI: %02x:%02x.%02x\r\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + printk_debug("%02x:", i); + } + val = pci_read_config8(dev, i); + printk_debug(" %02x", val); + if ((i & 0x0f) == 0x0f) { + printk_debug("\r\n"); + } + } +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + printk_debug("\r\ndimm %02x", device); + + for(i = 0; (i < 256) ; i++) { + if ((i % 16) == 0) { + printk_debug("\r\n%02x: ", i); + } + status = smbus_read_byte(device, i); + if (status < 0) { + printk_debug("bad device: %02x\r\n", -status); + break; + } + printk_debug("%02x ", status); + } + device += SMBUS_MEM_DEVICE_INC; + printk_debug("\r\n"); + } +} + +static void dump_mem(unsigned start, unsigned end) +{ + unsigned i; + print_debug("dump_mem:"); + for(i=start;i<end;i++) { + if((i & 0xf)==0) { +#if CONFIG_USE_INIT + printk_debug("\r\n%08x:", i); +#else + print_debug("\r\n"); + print_debug_hex32(i); + print_debug(":"); +#endif + } +#if CONFIG_USE_INIT + printk_debug(" %02x", (unsigned char)*((unsigned char *)i)); +#else + print_debug(" "); + print_debug_hex8((unsigned char)*((unsigned char *)i)); +#endif + } + print_debug("\r\n"); + } diff --git a/src/mainboard/kontron/986lcd-m/dmi.h b/src/mainboard/kontron/986lcd-m/dmi.h new file mode 100644 index 0000000000..29f697e03c --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/dmi.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define DMI_TABLE_SIZE 0x55 + +static u8 dmi_table[DMI_TABLE_SIZE] = { + 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, + 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, + 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, + 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, + 0x30, 0x30, 0x38, 0x00, 0x00 +}; diff --git a/src/mainboard/kontron/986lcd-m/dsdt.dsl b/src/mainboard/kontron/986lcd-m/dsdt.dsl new file mode 100644 index 0000000000..95627fb45d --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/dsdt.dsl @@ -0,0 +1,303 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT", "DSDT", 1, "986LCD", "COREBOOT", 0x0000001) +{ + Scope (\_PR) + { + Processor (CPU1, 0x01, 0x00000810, 0x06) + { + OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF) + Name (NCPU, 0x80) + Name (TYPE, 0x80000000) + Name (HNDL, 0x80000000) + Name (CFGD, 0x80000000) + Name (TBLD, 0x80) + Method (_PDC, 1, NotSerialized) + { + } + } + } + + Scope (\_PR) + { + Processor (CPU2, 0x02, 0x00000000, 0x00) + { + OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF) + Name (NCPU, 0x80) + Name (TYPE, 0x80000000) + Name (HNDL, 0x80000000) + Name (CFGD, 0x80000000) + Name (TBLD, 0x80) + Method (_PDC, 1, NotSerialized) + { + } + } + } + + Name (PICM, 0x00) + Method (_PIC, 1, NotSerialized) + { + Store (Arg0, PICM) + } + + Scope (\_SB) + { + Name (PR00, Package (0x12) + { + Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 }, + Package (0x04) { 0x001FFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x001FFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x03, LNKA, 0x00 }, + Package (0x04) { 0x001EFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0x001EFFFF, 0x01, LNKE, 0x00 }, + Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 } + }) + Name (AR00, Package (0x12) + { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x001FFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x17 }, + Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x001EFFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x001EFFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x10 } + }) + Name (PR01, Package (0x1D) + { + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, LNKF, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LNKG, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, LNKE, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, LNKG, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, LNKE, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, LNKF, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, LNKE, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, LNKF, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x01, LNKG, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x03, LNKE, 0x00 } + }) + Name (AR01, Package (0x1D) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x17 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x17 }, + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x14 } + }) + Name (PR04, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 } + }) + Name (AR04, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 0x13 } + }) + Name (PR05, Package (0x01) + { + Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 } + }) + Name (AR05, Package (0x01) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x11 } + }) + Name (PR06, Package (0x01) + { + Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 } + }) + Name (AR06, Package (0x01) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x12 } + }) + Name (PR07, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 } + }) + Name (AR07, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 0x12 } + }) + Name (PR08, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 } + }) + Name (AR08, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 0x13 } + }) + Name (PR09, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 } + }) + Name (AR09, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 0x10 } + }) + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x01) + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x02) + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x03) + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x04) + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x05) + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x06) + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x07) + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x08) + } + } + + Name (\_S0, Package (0x04) + { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S1, Package (0x04) + { 0x01, 0x00, 0x00, 0x00 }) + Name (\_S3, Package (0x04) + { 0x05, 0x00, 0x00, 0x00 }) + Name (\_S4, Package (0x04) + { 0x06, 0x00, 0x00, 0x00 }) + Name (\_S5, Package (0x04) + { 0x07, 0x00, 0x00, 0x00 }) +} + diff --git a/src/mainboard/kontron/986lcd-m/fadt.c b/src/mainboard/kontron/986lcd-m/fadt.c new file mode 100644 index 0000000000..3e8b45a876 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/fadt.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 132; + header->revision = 1; + memcpy(header->oem_id, "CORE ", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = 0; + fadt->sci_int = 0x9; + fadt->smi_cmd = 0xb2; + fadt->acpi_enable = 0xe1; + fadt->acpi_disable = 0x1e; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + fadt->flags = 0x80a5; + // wbinvd is operational + // all cpus support c1 + // sleep button is generic + // rtc wakeup/s4 not possible + + header->checksum = + acpi_checksum((void *) fadt, header->length); + +} diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c new file mode 100644 index 0000000000..6aa36bf026 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*18, /* There can be total 18 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xf, /* u8 checksum. */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} + diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c new file mode 100644 index 0000000000..17b23a2462 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_kontron_986lcd_m_ops = { + CHIP_NAME("Kontron 986LCD-M Mainboard") +}; + diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c new file mode 100644 index 0000000000..a239b3ff0c --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "986LCD-M "; + struct mp_config_table *mc; + int i; + int max_pci_bus, isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + max_pci_bus = 5; // XXX read me from bridges. + + /* ISA bus follows */ + isa_bus = max_pci_bus + 1; + + /* Bus: Bus ID Type */ + for (i=0; i <= max_pci_bus; i++) + smp_write_bus(mc, i, "PCI "); + + smp_write_bus(mc, isa_bus, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + + /* Legacy Interrupts */ + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf); + + /* Builtin devices on Bus 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); + + /* Firewire 4:0.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); + + // riser slot top 5:8.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); + // riser slot middle 5:9.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); + // riser slot bottom 5:a.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); + + /* Onboard Ethernet */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + + printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); + + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/kontron/986lcd-m/power_reset_check.c b/src/mainboard/kontron/986lcd-m/power_reset_check.c new file mode 100644 index 0000000000..53ec28f4bb --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/power_reset_check.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +static void power_down_reset_check(void) +{ + uint8_t cmos; + + cmos=cmos_read(RTC_BOOT_BYTE)>>4 ; + printk_debug("Boot byte = %x\r\n", cmos); + + if((cmos>2)&&(cmos&1)) full_reset(); +} diff --git a/src/mainboard/kontron/986lcd-m/reset.c b/src/mainboard/kontron/986lcd-m/reset.c new file mode 100644 index 0000000000..3e03a392bc --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/reset.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} + +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} diff --git a/src/mainboard/kontron/986lcd-m/rtl8168.c b/src/mainboard/kontron/986lcd-m/rtl8168.c new file mode 100644 index 0000000000..18f41fe32a --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/rtl8168.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void nic_init(struct device *dev) +{ + printk_debug("Initializing RTL8168 Gigabit Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver rtl8169_nic __pci_driver = { + .ops = &nic_ops, + .vendor = 0x10ec, + .device = 0x8168, +}; + + diff --git a/targets/kontron/986lcd-m/Config-abuild.lb b/targets/kontron/986lcd-m/Config-abuild.lb new file mode 100644 index 0000000000..fcae71e14d --- /dev/null +++ b/targets/kontron/986lcd-m/Config-abuild.lb @@ -0,0 +1,30 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +option ROM_SIZE=1024*(1024-64) +option FALLBACK_SIZE=1024*512 + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x19000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x19000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" + diff --git a/targets/kontron/986lcd-m/Config.lb b/targets/kontron/986lcd-m/Config.lb new file mode 100644 index 0000000000..df8e971b15 --- /dev/null +++ b/targets/kontron/986lcd-m/Config.lb @@ -0,0 +1,22 @@ +target kontron_986lcd_m +mainboard kontron/986lcd-m + +## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use +## (normal AND fallback images and payloads). +option ROM_SIZE = 1024*1024 + +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, +## not including any payload. +option ROM_IMAGE_SIZE = 0x20000 + +## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## (including payload) will use +option FALLBACK_SIZE = ROM_SIZE + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + #payload $(HOME)/filo.elf + payload /dev/zero +end + +buildrom ./linuxbios.rom ROM_SIZE "fallback" |