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-rw-r--r--src/northbridge/intel/sandybridge/early_init.c5
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c5
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h2
-rw-r--r--src/northbridge/intel/x4x/early_init.c9
-rw-r--r--src/northbridge/intel/x4x/romstage.c6
-rw-r--r--src/northbridge/intel/x4x/x4x.h2
6 files changed, 12 insertions, 17 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 42957e540b..b7ee3225ec 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -6,7 +6,6 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <option.h>
-#include <romstage_handoff.h>
#include <types.h>
#include "sandybridge.h"
@@ -194,9 +193,7 @@ void systemagent_early_init(void)
start_peg_link_training();
}
-void northbridge_romstage_finalize(int s3resume)
+void northbridge_romstage_finalize(void)
{
MCHBAR16(SSKPD_HI) = 0xCAFE;
-
- romstage_handoff_init(s3resume);
}
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 5c0dd5c1a7..fad8e2f91a 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -4,6 +4,7 @@
#include <cf9_reset.h>
#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
+#include <romstage_handoff.h>
#include <timestamp.h>
#include "sandybridge.h"
#include <arch/romstage.h>
@@ -75,7 +76,9 @@ void mainboard_romstage_entry(void)
post_code(0x3d);
- northbridge_romstage_finalize(s3resume);
+ northbridge_romstage_finalize();
post_code(0x3f);
+
+ romstage_handoff_init(s3resume);
}
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 27295955b1..63b51b0bc5 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -72,7 +72,7 @@ void intel_sandybridge_finalize_smm(void);
void systemagent_early_init(void);
void sandybridge_init_iommu(void);
void sandybridge_late_initialization(void);
-void northbridge_romstage_finalize(int s3resume);
+void northbridge_romstage_finalize(void);
void early_init_dmi(void);
/* mainboard_early_init: Optional callback, run after console init but before raminit. */
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index ea41e76dce..f942d59758 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -10,7 +10,6 @@
#include <option.h>
#include "x4x.h"
#include <console/console.h>
-#include <romstage_handoff.h>
void x4x_early_init(void)
{
@@ -216,14 +215,8 @@ static void init_dmi(void)
DMIBAR16(DMILCTL);
}
-static void x4x_prepare_resume(int s3resume)
-{
- romstage_handoff_init(s3resume);
-}
-
-void x4x_late_init(int s3resume)
+void x4x_late_init(void)
{
init_egress();
init_dmi();
- x4x_prepare_resume(s3resume);
}
diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c
index 648520c038..c70c1fb46c 100644
--- a/src/northbridge/intel/x4x/romstage.c
+++ b/src/northbridge/intel/x4x/romstage.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h>
+#include <romstage_handoff.h>
#include <southbridge/intel/common/pmclib.h>
#include <arch/romstage.h>
@@ -42,7 +43,8 @@ void mainboard_romstage_entry(void)
mb_get_spd_map(spd_addr_map);
sdram_initialize(boot_path, spd_addr_map);
- x4x_late_init(s3_resume);
-
+ x4x_late_init();
printk(BIOS_DEBUG, "x4x late init complete\n");
+
+ romstage_handoff_init(s3_resume);
}
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index b5842eef0d..c1177f05ef 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -157,7 +157,7 @@
#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */
void x4x_early_init(void);
-void x4x_late_init(int s3resume);
+void x4x_late_init(void);
void mb_get_spd_map(u8 spd_map[4]);
void mb_pre_raminit_setup(int s3_resume);
u32 decode_igd_memory_size(u32 gms);