diff options
| -rw-r--r-- | src/mainboard/advansus/a785e-i/mainboard.c | 11 | ||||
| -rw-r--r-- | src/mainboard/amd/bimini_fam10/mainboard.c | 14 | ||||
| -rw-r--r-- | src/mainboard/amd/mahogany_fam10/mainboard.c | 6 | ||||
| -rw-r--r-- | src/mainboard/amd/tilapia_fam10/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/asus/m4a78-em/mainboard.c | 8 | ||||
| -rw-r--r-- | src/mainboard/asus/m4a785-m/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/asus/m5a88-v/mainboard.c | 11 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/mainboard.c | 11 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ma785gm/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ma785gmt/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ma78gm/mainboard.c | 6 | ||||
| -rw-r--r-- | src/mainboard/iei/kino-780am2-fam10/mainboard.c | 11 | ||||
| -rw-r--r-- | src/mainboard/jetway/pa78vm5/mainboard.c | 7 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/cmn.c | 11 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/gfx.c | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.h | 2 |
16 files changed, 28 insertions, 101 deletions
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index b5a2ea82db..1381dfa352 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -23,9 +23,6 @@ #include <device/pci_def.h> #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); - /* GPIO6. */ static void enable_int_gfx(void) { @@ -45,14 +42,6 @@ static void enable_int_gfx(void) *(gpio_reg + 170) = 0x0; } -void set_pcie_dereset() -{ -} - -void set_pcie_reset(void) -{ -} - int is_dev3_present(void) { return 0; diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index b6347ebc37..3fa2405739 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -24,9 +24,6 @@ #include <southbridge/amd/sb800/sb800.h> #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); - /* GPIO6. */ static void enable_int_gfx(void) { @@ -58,16 +55,9 @@ static void enable_int_gfx(void) /* * Bimini uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. + * + * Old comment says: GPIO 50h to reset PCIe slot. ***/ -void set_pcie_dereset(void) -{ - /* GPIO 50h reset PCIe slot */ -} - -void set_pcie_reset(void) -{ - /* GPIO 50h reset PCIe slot */ -} int is_dev3_present(void) { diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 53a8290685..a4a26e026c 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -24,13 +24,11 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. ***/ -void set_pcie_dereset() +void set_pcie_dereset(void) { u16 word; struct device *sm_dev; @@ -43,7 +41,7 @@ void set_pcie_dereset() pci_write_config16(sm_dev, 0xA8, word); } -void set_pcie_reset() +void set_pcie_reset(void) { u16 word; struct device *sm_dev; diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index e8a08a53c1..44c1df69ba 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -34,10 +34,7 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -void set_pcie_dereset(void); -void set_pcie_reset(void); - -void set_pcie_dereset() +void set_pcie_dereset(void) { u8 byte; u16 word; @@ -62,7 +59,7 @@ void set_pcie_dereset() pci_write_config16(sm_dev, 0x7e, word); } -void set_pcie_reset() +void set_pcie_reset(void) { u8 byte; u16 word; diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index e80d39b0e8..87acc5674c 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -24,11 +24,7 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" - -void set_pcie_dereset(void); -void set_pcie_reset(void); - -void set_pcie_dereset() +void set_pcie_dereset(void) { u8 byte; u16 word; @@ -53,7 +49,7 @@ void set_pcie_dereset() pci_write_config16(sm_dev, 0x7e, word); } -void set_pcie_reset() +void set_pcie_reset(void) { u8 byte; u16 word; diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 42a9f644e3..5acce51969 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -34,10 +34,7 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -void set_pcie_dereset(void); -void set_pcie_reset(void); - -void set_pcie_dereset() +void set_pcie_dereset(void) { u8 byte; u16 word; @@ -62,7 +59,7 @@ void set_pcie_dereset() pci_write_config16(sm_dev, 0x7e, word); } -void set_pcie_reset() +void set_pcie_reset(void) { u8 byte; u16 word; diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 4ec716e96a..75f231e74b 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -23,9 +23,6 @@ #include <device/pci_def.h> #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); - /* GPIO6. */ static void enable_int_gfx(void) { @@ -45,14 +42,6 @@ static void enable_int_gfx(void) *(gpio_reg + 170) = 0x0; } -void set_pcie_dereset() -{ -} - -void set_pcie_reset(void) -{ -} - int is_dev3_present(void) { return 0; diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 4d2f0ff42d..79564a288f 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -23,9 +23,6 @@ #include <device/pci_def.h> #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); - /* GPIO6. */ static void enable_int_gfx(void) { @@ -45,14 +42,6 @@ static void enable_int_gfx(void) *(gpio_reg + 170) = 0x0; } -void set_pcie_dereset() -{ -} - -void set_pcie_reset(void) -{ -} - int is_dev3_present(void) { return 1; diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 37a3828f94..8fbc591c86 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -24,10 +24,7 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); - -void set_pcie_dereset() +void set_pcie_dereset(void) { u8 byte; u16 word; @@ -52,7 +49,7 @@ void set_pcie_dereset() pci_write_config16(sm_dev, 0x7e, word); } -void set_pcie_reset() +void set_pcie_reset(void) { u8 byte; u16 word; diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index ce186bf587..48545a4535 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -34,10 +34,7 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -void set_pcie_dereset(void); -void set_pcie_reset(void); - -void set_pcie_dereset() +void set_pcie_dereset(void) { u8 byte; u16 word; @@ -62,7 +59,7 @@ void set_pcie_dereset() pci_write_config16(sm_dev, 0x7e, word); } -void set_pcie_reset() +void set_pcie_reset(void) { u8 byte; u16 word; diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 3e73f229e9..bfd083497e 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -25,13 +25,11 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); /* * ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. ***/ -void set_pcie_dereset() +void set_pcie_dereset(void) { u16 word; struct device *sm_dev; @@ -44,7 +42,7 @@ void set_pcie_dereset() pci_write_config16(sm_dev, 0xA8, word); } -void set_pcie_reset() +void set_pcie_reset(void) { u16 word; struct device *sm_dev; diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index f75bec2f9f..b0ffef71f2 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -24,21 +24,10 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); /* TODO - Need to find GPIO for PCIE slot. * Kino uses GPIO ? as PCIe slot reset, GPIO? as GFX slot reset. We need to * pull it up before training the slot. ***/ -void set_pcie_dereset() -{ - /* PCIE slot not yet supported.*/ -} - -void set_pcie_reset() -{ - /* PCIE slot not yet supported.*/ -} int is_dev3_present(void) { diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 906b070569..9585832ebe 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -25,14 +25,11 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); - /* * the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. ***/ -void set_pcie_dereset() +void set_pcie_dereset(void) { u16 word; struct device *sm_dev; @@ -45,7 +42,7 @@ void set_pcie_dereset() pci_write_config16(sm_dev, 0xA8, word); } -void set_pcie_reset() +void set_pcie_reset(void) { u16 word; struct device *sm_dev; diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index c39c6e9968..b849e1efa7 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -256,9 +256,6 @@ u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port) u32 lc_state, reg, current_link_width, lane_mask; int8_t current, res = 0; u32 gfx_gpp_sb_sel; - void set_pcie_dereset(void); - void set_pcie_reset(void); - switch (port) { case 2 ... 3: gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX; @@ -397,3 +394,11 @@ int is_family10h(void) { return cpuidFamily() == 0x10; } + +__weak void set_pcie_reset(void) +{ +} + +__weak void set_pcie_dereset(void) +{ +} diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 3152a14eb1..cfcddb29f3 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -36,9 +36,6 @@ #include <cpu/x86/msr.h> #include "rs780.h" -void set_pcie_reset(void); -void set_pcie_dereset(void); - /* Trust the original resource allocation. Don't do it again. */ #undef DONT_TRUST_RESOURCE_ALLOCATION //#define DONT_TRUST_RESOURCE_ALLOCATION diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index a8bbbe2231..ce46d96760 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -223,5 +223,7 @@ void enable_rs780_dev8(void); void rs780_early_setup(void); void rs780_htinit(void); int is_dev3_present(void); +void set_pcie_reset(void); +void set_pcie_dereset(void); #endif /* __RS780_H__ */ |