diff options
| -rw-r--r-- | src/southbridge/via/vt8231/Config.lb | 2 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/chip.h | 14 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231.c | 359 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231.h | 195 |
4 files changed, 570 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8231/Config.lb b/src/southbridge/via/vt8231/Config.lb new file mode 100644 index 0000000000..adaa1218e9 --- /dev/null +++ b/src/southbridge/via/vt8231/Config.lb @@ -0,0 +1,2 @@ +config chip.h +object w83c553f.o diff --git a/src/southbridge/via/vt8231/chip.h b/src/southbridge/via/vt8231/chip.h new file mode 100644 index 0000000000..5c2d67a78f --- /dev/null +++ b/src/southbridge/via/vt8231/chip.h @@ -0,0 +1,14 @@ +#ifndef _SOUTHBRIDGE_VIA_VT8231 +#define _SOUTHBRIDGE_VIA_VT8231 + +extern struct chip_control southbridge_via_vt8231_control; + +struct southbridge_via_vt8231_config { + int enable_usb; + int enable_native_ide; + int enable_com_ports; + int enable_keyboard; + int enable_nvram; +}; + +#endif /* _SOUTHBRIDGE_VIA_VT8231 */ diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c new file mode 100644 index 0000000000..d1bb66ba64 --- /dev/null +++ b/src/southbridge/via/vt8231/vt8231.c @@ -0,0 +1,359 @@ + +#include <arch/io.h> +#include <device/pci.h> +#include <device/chip.h> +#include <console/console.h> +#include "vt8231.h" +#include "chip.h" + + + +void usb_on(int enable) +{ + unsigned char regval; + + /* Base 8231 controller */ + struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231, 0); + /* USB controller 1 */ + struct pci_dev *dev2 = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_82C586_2, 0); + /* USB controller 2 */ + struct pci_dev *dev3 = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_82C586_2, \ + dev2); + + /* enable USB1 */ + if(dev2) { + if (enable) { + pci_write_config_byte(dev2, 0x3c, 0x05); + pci_write_config_byte(dev2, 0x04, 0x07); + } else { + pci_write_config_byte(dev2, 0x3c, 0x00); + pci_write_config_byte(dev2, 0x04, 0x00); + } + } + + if(dev0) { + pci_read_config_byte(dev0, 0x50, ®val); + if (enable) + regval &= ~(0x10); + else + regval |= 0x10; + pci_write_config_byte(dev0, 0x50, regval); + } + + /* enable USB2 */ + if(dev3) { + if (enable) { + pci_write_config_byte(dev3, 0x3c, 0x05); + pci_write_config_byte(dev3, 0x04, 0x07); + } else { + pci_write_config_byte(dev3, 0x3c, 0x00); + pci_write_config_byte(dev3, 0x04, 0x00); + } + } + + if(dev0) { + pci_read_config_byte(dev0, 0x50, ®val); + if (enable) + regval &= ~(0x20); + else + regval |= 0x20; + pci_write_config_byte(dev0, 0x50, regval); + } + +} + +void keyboard_on() +{ + unsigned char regval; + + /* Base 8231 controller */ + struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231, 0); + + /* kevinh/Ispiri - update entire function to use + new pci_write_config_byte */ + + if (dev0) { + pci_read_config_byte(dev0, 0x51, ®val); + regval |= 0x0f; + pci_write_config_byte(dev0, 0x51, regval); + } + pc_keyboard_init(); + +} + +void nvram_on() +{ + /* + * the VIA 8231 South has a very different nvram setup than the + * piix4e ... + * turn on ProMedia nvram. + * TO DO: use the PciWriteByte function here. + */ + + /* + * kevinh/Ispiri - I don't think this is the correct address/value + * intel_conf_writeb(0x80008841, 0xFF); + */ +} + + +/* + * Enable the ethernet device and turn off stepping (because it is integrated + * inside the southbridge) + */ +void ethernet_fixup() +{ + struct pci_dev *dev, *edev; + u8 byte; + + printk_info("Ethernet fixup\n"); + + edev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0); + if (edev != NULL) { + printk_debug("Configuring VIA LAN\n"); + + /* We don't need stepping - though the device supports it */ + pci_read_config_byte(edev, PCI_COMMAND, &byte); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config_byte(edev, PCI_COMMAND, byte); + } else { + printk_debug("VIA LAN not found\n"); + } +} + + +void southbridge_fixup() +{ + unsigned char enables; + struct pci_dev *dev0; + struct pci_dev *dev1; + struct pci_dev *devpwr; + + // to do: use the pcibios_find function here, instead of + // hard coding the devfn. + // done - kevinh/Ispiri + + /* Base 8231 controller */ + dev0 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + /* IDE controller */ + dev1 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \ + 0); + /* Power management controller */ + devpwr = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231_4, 0); + + // enable the internal I/O decode + enables = pci_read_config_byte(dev0, 0x6C, &enables); + enables |= 0x80; + pci_write_config_byte(dev0, 0x6C, enables); + + // Map 4MB of FLASH into the address space + pci_write_config_byte(dev0, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config_byte(dev0, 0x40, &enables); enables |= 0x44; + pci_write_config_byte(dev0, 0x40, enables); + + // Set 0x42 to 0xf0 to match Award bios + enables = pci_read_config_byte(dev0, 0x42, &enables); + enables |= 0xf0; + pci_write_config_byte(dev0, 0x42, enables); + + // Set bit 3 of 0x4a, to match award (dummy pci request) + enables = pci_read_config_byte(dev0, 0x4a, &enables); + enables |= 0x08; + pci_write_config_byte(dev0, 0x4a, enables); + + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) + enables = pci_read_config_byte(dev0, 0x4f, &enables); + enables |= 0x08; + pci_write_config_byte(dev0, 0x4f, enables); + + // Set 0x58 to 0x03 to match Award + pci_write_config_byte(dev0, 0x58, 0x03); + + // enable the ethernet/RTC + if(dev0) { + pci_read_config_byte(dev0, 0x51, &enables); + enables |= 0x18; + pci_write_config_byte(dev0, 0x51, enables); + } + + + // enable com1 and com2. + if (conf->enable_com_ports) { + enables = pci_read_config_byte(dev0, 0x6e, &enables); + /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 + * is enable com port a as com1 kevinh/Ispiri - Old code + * thought 0x01 would make it com1, that was wrong /* + * enables = 0x80 | 0x10 | 0x8 ; pci_write_config_byte(dev0, + * 0x6e, enables); // note: this is also a redo of some port + * of assembly, but we want everything up. + */ + + /* set com1 to 115 kbaud not clear how to do this yet. + * forget it; done in assembly. + */ +#endif + + // enable IDE, since Linux won't do it. + // First do some more things to devfn (17,0) + // note: this should already be cleared, according to the book. + pci_read_config_byte(dev0, 0x50, &enables); + printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); + enables &= ~8; // need manifest constant here! + printk_debug("set IDE reg. 50 to 0x%x\n", enables); + pci_write_config_byte(dev0, 0x50, enables); + + // set default interrupt values (IDE) + pci_read_config_byte(dev0, 0x4c, &enables); + printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); + // clear out whatever was there. + enables &= ~0xf; + enables |= 4; + printk_debug("setting reg. 4c to 0x%x\n", enables); + pci_write_config_byte(dev0, 0x4c, enables); + + // set up the serial port interrupts. + // com2 to 3, com1 to 4 + pci_write_config_byte(dev0, 0x46, 0x04); + pci_write_config_byte(dev0, 0x47, 0x03); + + // + // Power management setup + // + // Set ACPI base address to IO 0x4000 + pci_write_config_dword(devpwr, 0x48, 0x4001); + + // Enable ACPI access (and setup like award) + pci_write_config_byte(devpwr, 0x41, 0x84); + + // Set hardware monitor base address to IO 0x6000 + pci_write_config_dword(devpwr, 0x70, 0x6001); + + // Enable hardware monitor (and setup like award) + pci_write_config_byte(devpwr, 0x74, 0x01); + + // set IO base address to 0x5000 + pci_write_config_dword(devpwr, 0x90, 0x5001); + + // Enable SMBus + pci_write_config_byte(devpwr, 0xd2, 0x01); + + // + // IDE setup + // + if (conf->enable_native_ide) { + // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI + // interrupts. Using PCI ints confuses linux for some reason. + + pci_read_config_byte(dev1, 0x42, &enables); + printk_debug("enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config_byte(dev1, 0x42, enables); + pci_read_config_byte(dev1, 0x42, &enables); + printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); + } + + pci_read_config_byte(dev1, 0x40, &enables); + printk_debug("enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config_byte(dev1, 0x40, enables); + pci_read_config_byte(dev1, 0x40, &enables); + printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + + // Enable prefetch buffers + pci_read_config_byte(dev1, 0x41, &enables); + enables |= 0xf0; + pci_write_config_byte(dev1, 0x41, enables); + + // Lower thresholds (cause award does it) + pci_read_config_byte(dev1, 0x43, &enables); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config_byte(dev1, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config_byte(dev1, 0x44, 0x18); + + // Use memory read multiple + pci_write_config_byte(dev1, 0x45, 0x1c); + + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + pci_read_config_byte(dev1, 0x9, &enables); + printk_debug("enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + if (conf->enable_native_ide) { + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + } else { + enables &= ~0x5; + } + + pci_write_config_byte(dev1, 0x9, enables); + pci_read_config_byte(dev1, 0x9, &enables); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + pci_read_config_byte(dev1, 0x4, &enables); + printk_debug("command in reg 0x4 0x%x\n", enables); + enables |= 7; + + // No need for stepping - kevinh@ispiri.com + enables &= ~0x80; + + pci_write_config_byte(dev1, 0x4, enables); + pci_read_config_byte(dev1, 0x4, &enables); + printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); + + if (! conf->enable_native_ide) { + // Use compatability mode - per award bios + pci_write_config_dword(dev1, 0x10, 0x0); + pci_write_config_dword(dev1, 0x14, 0x0); + pci_write_config_dword(dev1, 0x18, 0x0); + pci_write_config_dword(dev1, 0x1c, 0x0); + + // Force interrupts to use compat mode - just like Award bios + pci_write_config_byte(dev1, 0x3d, 00); + pci_write_config_byte(dev1, 0x3c, 0xff); + } + + + ethernet_fixup(); + + // Start the rtc + rtc_init(0); +} + +static void +southbridge_init(struct chip *chip, enum chip_pass pass) +{ + + struct southbridge_via_vt8231_config *conf = + (struct southbridge_via_vt8231_config *)chip->chip_info; + + switch (pass) { + case CONF_PASS_POST_PCI: + vt8231_init(conf); + break; + + default: + /* nothing yet */ + break; + } +} + +struct chip_control southbridge_via_vt8231_control = { + enable: southbridge_init, + name: "VIA vt8231" +}; diff --git a/src/southbridge/via/vt8231/vt8231.h b/src/southbridge/via/vt8231/vt8231.h new file mode 100644 index 0000000000..f071371938 --- /dev/null +++ b/src/southbridge/via/vt8231/vt8231.h @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + /* winbond access routines and defines*/ + +/* from the winbond data sheet - + The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. + Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. +*/ + +/*ISA bridge configuration space*/ + +#define W83C553F_VID 0x10AD +#define W83C553F_DID 0x0565 +#define W83C553F_IDE 0x0105 + +/* Function 0 registers */ +#define W83C553F_PCICONTR 0x40 /*pci control reg*/ +#define W83C553F_SGBAR 0x41 /*scatter/gather base address reg*/ +#define W83C553F_LBCR 0x42 /*Line Buffer Control reg*/ +#define W83C553F_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ +#define W83C553F_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ +#define W83C553F_BTBAR 0x46 /*BIOS Timer Base Address Register*/ +#define W83C553F_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ +#define W83C553F_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ +#define W83C553F_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ +#define W83C553F_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ +#define W83C553F_CDR 0x4c /*Clock Divisor Register*/ +#define W83C553F_CSCR 0x4d /*Chip Select Control Register*/ +#define W83C553F_ATSCR 0x4e /*AT System Control register*/ +#define W83C553F_ATBCR 0x4f /*AT Bus ControL Register*/ +#define W83C553F_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ +#define W83C553F_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ +#define W83C553F_ABEER 0x62 /*Additional Break Event Enable Register*/ +#define W83C553F_DMABEER 0x63 /*DMA Break Event Enable Register*/ + +/* Function 1 registers */ +#define W83C553F_PIR 0x09 /*Programming Interface Register*/ +#define W83C553F_IDECSR 0x40 /*IDE Control/Status Register*/ + +/* register bit definitions */ +#define W83C553F_IPADCR_MBE512 0x1 +#define W83C553F_IPADCR_MBE640 0x2 +#define W83C553F_IPADCR_IPATOM4 0x10 +#define W83C553F_IPADCR_IPATOM5 0x20 +#define W83C553F_IPADCR_IPATOM6 0x40 +#define W83C553F_IPADCR_IPATOM7 0x80 + +#define W83C553F_CSCR_UBIOSCSE 0x10 +#define W83C553F_CSCR_BIOSWP 0x20 + +#define W83C553F_IDECSR_P0EN 0x01 +#define W83C553F_IDECSR_P0F16 0x02 +#define W83C553F_IDECSR_P1EN 0x10 +#define W83C553F_IDECSR_P1F16 0x20 +#define W83C553F_IDECSR_LEGIRQ 0x800 + +#define W83C553F_ATSCR_ISARE 0x40 +#define W83C553F_ATSCR_FERRE 0x10 +#define W83C553F_ATSCR_P92E 0x04 +#define W83C553F_ATSCR_KRCEE 0x02 +#define W83C553F_ATSCR_KGA20EE 0x01 + +#define W83C553F_PIR_BM 0x80 +#define W83C553F_PIR_P1PROG 0x08 +#define W83C553F_PIR_P1NL 0x04 +#define W83C553F_PIR_P0PROG 0x02 +#define W83C553F_PIR_P0NL 0x01 + +/* + * Interrupt controller + */ +#define W83C553F_PIC1_ICW1 CONFIG_ISA_IO + 0x20 +#define W83C553F_PIC1_ICW2 CONFIG_ISA_IO + 0x21 +#define W83C553F_PIC1_ICW3 CONFIG_ISA_IO + 0x21 +#define W83C553F_PIC1_ICW4 CONFIG_ISA_IO + 0x21 +#define W83C553F_PIC1_OCW1 CONFIG_ISA_IO + 0x21 +#define W83C553F_PIC1_OCW2 CONFIG_ISA_IO + 0x20 +#define W83C553F_PIC1_OCW3 CONFIG_ISA_IO + 0x20 +#define W83C553F_PIC1_ELC CONFIG_ISA_IO + 0x4D0 +#define W83C553F_PIC2_ICW1 CONFIG_ISA_IO + 0xA0 +#define W83C553F_PIC2_ICW2 CONFIG_ISA_IO + 0xA1 +#define W83C553F_PIC2_ICW3 CONFIG_ISA_IO + 0xA1 +#define W83C553F_PIC2_ICW4 CONFIG_ISA_IO + 0xA1 +#define W83C553F_PIC2_OCW1 CONFIG_ISA_IO + 0xA1 +#define W83C553F_PIC2_OCW2 CONFIG_ISA_IO + 0xA0 +#define W83C553F_PIC2_OCW3 CONFIG_ISA_IO + 0xA0 +#define W83C553F_PIC2_ELC CONFIG_ISA_IO + 0x4D1 + +#define W83C553F_TMR1_CMOD CONFIG_ISA_IO + 0x43 + +/* + * DMA controller + */ +#define W83C553F_DMA1 CONFIG_ISA_IO + 0x000 /* channel 0 - 3 */ +#define W83C553F_DMA2 CONFIG_ISA_IO + 0x0C0 /* channel 4 - 7 */ + +/* command/status register bit definitions */ + +#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ +#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ +#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ +#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ + +#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ +#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ +#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ +#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ + +#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ +#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ +#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ +#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ + +/* mode register bit definitions */ + +#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ +#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ +#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ +#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ +#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ +#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ +#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ +#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ +#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ +#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ +#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* request register bit definitions */ + +#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ +#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* write single mask bit register bit definitions */ + +#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ +#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* read/write all mask bits register bit definitions */ + +#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ +#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ +#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ +#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ + +/* typedefs */ + +#define W83C553F_DMA1_CS 0x8 +#define W83C553F_DMA1_WR 0x9 +#define W83C553F_DMA1_WSMB 0xA +#define W83C553F_DMA1_WM 0xB +#define W83C553F_DMA1_CBP 0xC +#define W83C553F_DMA1_MC 0xD +#define W83C553F_DMA1_CM 0xE +#define W83C553F_DMA1_RWAMB 0xF + +#define W83C553F_DMA2_CS 0xD0 +#define W83C553F_DMA2_WR 0xD2 +#define W83C553F_DMA2_WSMB 0xD4 +#define W83C553F_DMA2_WM 0xD6 +#define W83C553F_DMA2_CBP 0xD8 +#define W83C553F_DMA2_MC 0xDA +#define W83C553F_DMA2_CM 0xDC +#define W83C553F_DMA2_RWAMB 0xDE + +void initialise_w83c553f(void); |