diff options
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 06ef898ca5..9f8a7d2f4b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -32,6 +32,8 @@ #define PSP_MAILBOX_BAR_EN 0x10 /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_DECODE_EN 0x00 +#define CF9_IO_EN BIT(1) #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c46bcb44a6..591a8f7c9f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -368,6 +368,13 @@ void sb_acpi_mmio_decode(void) outb(byte, PM_DATA); } +static void sb_enable_cf9_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); +} + void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -542,6 +549,7 @@ void bootblock_fch_early_init(void) sb_spibase(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); + sb_enable_cf9_io(); enable_aoac_devices(); } |