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-rw-r--r--src/mainboard/intel/dcp847ske/early_southbridge.c10
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c28
-rw-r--r--src/southbridge/intel/bd82x6x/pch.c2
3 files changed, 28 insertions, 12 deletions
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 1f76db8e52..34310a0094 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -33,16 +33,6 @@ void mainboard_late_rcba_config(void)
/* Disable devices */
RCBA32(FD) |= PCH_DISABLE_P2P;
-#if CONFIG(USE_NATIVE_RAMINIT)
- /* Enable Gigabit Ethernet */
- if (RCBA32(BUC) & PCH_DISABLE_GBE) {
- RCBA32(BUC) &= ~PCH_DISABLE_GBE;
- /* Datasheet says clearing the bit requires a reset after */
- printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n");
- full_reset();
- }
-#endif
-
/* Set "mobile" bit in MCH (which makes sense layout-wise). */
/* Note sure if this has any effect at all though. */
MCHBAR32(0x0004) |= 0x00001000;
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 8ffb22e140..b12ad38f47 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -16,6 +16,7 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <arch/cbfs.h>
+#include <cf9_reset.h>
#include <ip_checksum.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/gpio.h>
@@ -253,6 +254,30 @@ static void pch_generic_setup(void)
write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */
}
+static void pch_enable_gbe(void)
+{
+ uint8_t wanted_buc;
+
+ /* Don't do this in the bootblock, it might be RO. So one
+ couldn't change the setting later in an updated romstage. */
+ if (ENV_BOOTBLOCK)
+ return;
+
+ const struct device *const gbe = pcidev_on_root(0x19, 0);
+ if (gbe && gbe->enabled)
+ wanted_buc = RCBA8(BUC) & ~PCH_DISABLE_GBE;
+ else
+ wanted_buc = RCBA8(BUC) | PCH_DISABLE_GBE;
+
+ if (RCBA8(BUC) != wanted_buc) {
+ RCBA8(BUC) = wanted_buc;
+ /* Be double sure not to reset for naught. */
+ if (RCBA8(BUC) != wanted_buc)
+ return;
+ full_reset();
+ }
+}
+
static void pch_enable_lpc_decode(void)
{
/*
@@ -292,7 +317,6 @@ __weak void mainboard_pch_lpc_setup(void)
void early_pch_init(void)
{
-
pch_enable_lpc_decode();
mainboard_pch_lpc_setup();
@@ -301,5 +325,7 @@ void early_pch_init(void)
pch_generic_setup();
+ pch_enable_gbe();
+
setup_pch_gpios(&mainboard_gpio_map);
}
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 3cd39a6706..5c2b130b7e 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -166,7 +166,7 @@ static void pch_hide_devfn(unsigned int devfn)
RCBA32_OR(FD2, PCH_DISABLE_KT);
break;
case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
- RCBA32_OR(BUC, PCH_DISABLE_GBE);
+ /* BUC is already handled in `early_pch.c`. */
break;
case PCI_DEVFN(26, 0): /* EHCI #2 */
RCBA32_OR(FD, PCH_DISABLE_EHCI2);