diff options
| -rw-r--r-- | src/soc/intel/elkhartlake/acpi/gpio.asl | 18 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/gpio.c | 116 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/gpio.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/gpio_defs.h | 484 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h | 686 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/pcr_ids.h | 1 |
6 files changed, 757 insertions, 555 deletions
diff --git a/src/soc/intel/elkhartlake/acpi/gpio.asl b/src/soc/intel/elkhartlake/acpi/gpio.asl index 27cb503f45..fa3ef57ec7 100644 --- a/src/soc/intel/elkhartlake/acpi/gpio.asl +++ b/src/soc/intel/elkhartlake/acpi/gpio.asl @@ -18,6 +18,7 @@ Device (GPIO) Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM1) Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM3) Memory32Fixed (ReadWrite, 0, 0, COM4) Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) @@ -44,6 +45,12 @@ Device (GPIO) BAS2 = ^^PCRB (PID_GPIOCOM2) LEN2 = GPIO_BASE_SIZE + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE + /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) @@ -88,13 +95,19 @@ Method (GADD, 1, NotSerialized) Local0 = PID_GPIOCOM2 Local1 = Arg0 - GPIO_COM2_START } + /* GPIO Community 3 */ + If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END) + { + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPIO_COM3_START + } /* GPIO Community 4 */ If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) { Local0 = PID_GPIOCOM4 Local1 = Arg0 - GPIO_COM4_START } - /* GPIO Community 05*/ + /* GPIO Community 5 */ If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) { Local0 = PID_GPIOCOM5 @@ -123,6 +136,9 @@ Method (GPID, 1, Serialized) Case (COMM_2) { Local0 = PID_GPIOCOM2 } + Case (COMM_3) { + Local0 = PID_GPIOCOM3 + } Case (COMM_4) { Local0 = PID_GPIOCOM4 } diff --git a/src/soc/intel/elkhartlake/gpio.c b/src/soc/intel/elkhartlake/gpio.c index 9ba5d8e058..452f7cfbf2 100644 --- a/src/soc/intel/elkhartlake/gpio.c +++ b/src/soc/intel/elkhartlake/gpio.c @@ -32,48 +32,50 @@ static const struct reset_mapping rst_map_com0[] = { * linux/drivers/pinctrl/intel/pinctrl-elkhartlake.c */ static const struct pad_group ehl_community0_groups[] = { - - INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0), /* GPP_F */ - INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8), - INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ - INTEL_GPP(GPP_F0, GPIO_RSVD_9, GPIO_RSVD_10), - INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */ - INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ - INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B23, 0), /* GPP_B */ + INTEL_GPP(GPP_B0, GPIO_RSVD_0, GPIO_RSVD_1), + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_G0, GPIO_RSVD_2, 64), /* GPP_G */ }; static const struct pad_group ehl_community1_groups[] = { - INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */ - INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192), /* GPP_D */ - INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13), - INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ - INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */ + INTEL_GPP_BASE(GPP_V0, GPP_V0, GPP_V15, 96), /* GPP_V */ + INTEL_GPP_BASE(GPP_V0, GPP_H0, GPP_H23, 128), /* GPP_H */ + INTEL_GPP_BASE(GPP_V0, GPP_D0, GPIO_RSVD_3, 160), /* GPP_D */ + INTEL_GPP_BASE(GPP_V0, GPP_U0, GPP_U19, 192), /* GPP_U */ + INTEL_GPP(GPP_V0, GPIO_RSVD_4, GPIO_RSVD_7), + INTEL_GPP_BASE(GPP_V0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ }; /* This community is not visible to the OS */ static const struct pad_group ehl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD10), /* GPD */ - INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17), + INTEL_GPP(GPD0, GPD0, GPIO_RSVD_12), /* GPD */ }; +static const struct pad_group ehl_community3_groups[] = { + INTEL_GPP(GPIO_RSVD_13, GPIO_RSVD_13, GPIO_RSVD_29), + INTEL_GPP_BASE(GPIO_RSVD_13, GPP_S0, GPP_S1, 288), /* GPP_S */ + INTEL_GPP_BASE(GPIO_RSVD_13, GPP_A0, GPP_A23, 320), /* GPP_A */ + INTEL_GPP(GPIO_RSVD_13, VGPIO_USB_0, VGPIO_USB_3), +}; static const struct pad_group ehl_community4_groups[] = { - INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23), - INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288), /* GPP_E */ - INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36), + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 352), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F23, 384), /* GPP_F */ + INTEL_GPP(GPP_C0, GPIO_RSVD_30, GPIO_RSVD_36), + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 416), /* GPP_E */ }; - static const struct pad_group ehl_community5_groups[] = { - INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320), /* GPP_G */ + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 448), /* GPP_R */ }; static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = { - /* GPP F, B, A, S, R */ + /* GPP B, T, G */ [COMM_0] = { .port = PID_GPIOCOM0, - .first_pad = GPP_F0, - .last_pad = GPP_R7, + .first_pad = GPIO_COM0_START, + .last_pad = GPIO_COM0_END, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -82,18 +84,18 @@ static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = { .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_FBASR", + .name = "GPP_BTG", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map_com0, .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = ehl_community0_groups, .num_groups = ARRAY_SIZE(ehl_community0_groups), }, - /* GPP H, D, VGPIO, C */ + /* GPP V, H, D, U, VGPIO */ [COMM_1] = { .port = PID_GPIOCOM1, - .first_pad = GPP_H0, - .last_pad = GPP_C23, + .first_pad = GPIO_COM1_START, + .last_pad = GPIO_COM1_END, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -102,7 +104,7 @@ static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = { .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_HDC", + .name = "GPP_VHDU", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), @@ -112,8 +114,8 @@ static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = { /* GPD */ [COMM_2] = { .port = PID_GPIOCOM2, - .first_pad = GPD0, - .last_pad = GPIO_RSVD_17, + .first_pad = GPIO_COM2_START, + .last_pad = GPIO_COM2_END, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -129,11 +131,31 @@ static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = { .groups = ehl_community2_groups, .num_groups = ARRAY_SIZE(ehl_community2_groups), }, - /* GPP E */ + /* GPP S, A */ + [COMM_3] = { + .port = PID_GPIOCOM3, + .first_pad = GPIO_COM3_START, + .last_pad = GPIO_COM3_END, + .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SA", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ehl_community3_groups, + .num_groups = ARRAY_SIZE(ehl_community3_groups), + }, + /* GPP C, F, E */ [COMM_4] = { .port = PID_GPIOCOM4, - .first_pad = GPIO_RSVD_18, - .last_pad = GPIO_RSVD_36, + .first_pad = GPIO_COM4_START, + .last_pad = GPIO_COM4_END, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -142,18 +164,18 @@ static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = { .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_E", + .name = "GPP_CFE", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = ehl_community4_groups, .num_groups = ARRAY_SIZE(ehl_community4_groups), }, - /* GPP G */ + /* GPP R*/ [COMM_5] = { .port = PID_GPIOCOM5, - .first_pad = GPP_G0, - .last_pad = GPP_G7, + .first_pad = GPIO_COM5_START, + .last_pad = GPIO_COM5_END, .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -162,7 +184,7 @@ static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = { .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_G", + .name = "GPP_RR", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), @@ -180,17 +202,21 @@ const struct pad_community *soc_gpio_get_community(size_t *num_communities) const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) { static const struct pmc_to_gpio_route routes[] = { - { PMC_GPP_A, GPP_A }, { PMC_GPP_B, GPP_B }, - { PMC_GPP_G, GPP_G }, - { PMC_GPP_C, GPP_C }, - { PMC_GPP_R, GPP_R }, + { PMC_GPP_T, GPP_T }, { PMC_GPP_D, GPP_D }, - { PMC_GPP_S, GPP_S }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_V, GPP_V }, + { PMC_GPD, GPD }, { PMC_GPP_H, GPP_H }, + { PMC_GPP_U, GPP_U }, + { PMC_VGPIO, VGPIO }, { PMC_GPP_F, GPP_F }, - { PMC_GPD, GPP_GPD }, - { PMC_GPP_E, GPP_E } + { PMC_GPP_C, GPP_C }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_G, GPP_G }, + { PMC_GPP_S, GPP_S } }; *num = ARRAY_SIZE(routes); diff --git a/src/soc/intel/elkhartlake/include/soc/gpio.h b/src/soc/intel/elkhartlake/include/soc/gpio.h index 47f792caec..1eac393986 100644 --- a/src/soc/intel/elkhartlake/include/soc/gpio.h +++ b/src/soc/intel/elkhartlake/include/soc/gpio.h @@ -6,11 +6,8 @@ #include <soc/gpio_defs.h> #include <intelblocks/gpio.h> -#define CROS_GPIO_NAME "INT34C8" -#define CROS_GPIO_COMM0_NAME "INT34C8:00" -#define CROS_GPIO_COMM1_NAME "INT34C8:01" -#define CROS_GPIO_COMM4_NAME "INT34C8:02" -#define CROS_GPIO_COMM5_NAME "INT34C8:03" +#define CROS_GPIO_NAME "INTC1020" +#define CROS_GPIO_DEVICE_NAME "INTC1020:00" /* Enable GPIO community power management configuration */ #define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \ diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_defs.h index 0b8d8a74a9..52c83dc975 100644 --- a/src/soc/intel/elkhartlake/include/soc/gpio_defs.h +++ b/src/soc/intel/elkhartlake/include/soc/gpio_defs.h @@ -17,6 +17,7 @@ #define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) #define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) #define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) @@ -24,237 +25,312 @@ ((NUM_GPIO_COM0_GPI_REGS) +\ (NUM_GPIO_COM1_GPI_REGS) +\ (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ (NUM_GPIO_COM4_GPI_REGS) +\ (NUM_GPIO_COM5_GPI_REGS)) /* * IOxAPIC IRQs for the GPIOs */ -/* Group F */ -#define GPP_F0_IRQ 0x40 -#define GPP_F1_IRQ 0x41 -#define GPP_F2_IRQ 0x42 -#define GPP_F3_IRQ 0x43 -#define GPP_F4_IRQ 0x44 -#define GPP_F5_IRQ 0x45 -#define GPP_F6_IRQ 0x46 -#define GPP_F7_IRQ 0x47 -#define GPP_F8_IRQ 0x48 -#define GPP_F9_IRQ 0x49 -#define GPP_F10_IRQ 0x4a -#define GPP_F11_IRQ 0x4b -#define GPP_F12_IRQ 0x4c -#define GPP_F13_IRQ 0x4d -#define GPP_F14_IRQ 0x4e -#define GPP_F15_IRQ 0x4f -#define GPP_F16_IRQ 0x50 -#define GPP_F17_IRQ 0x51 -#define GPP_F18_IRQ 0x52 -#define GPP_F19_IRQ 0x53 +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11_IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F /* Group G */ -#define GPP_G0_IRQ 0x18 -#define GPP_G1_IRQ 0x19 -#define GPP_G2_IRQ 0x1a -#define GPP_G3_IRQ 0x1b -#define GPP_G4_IRQ 0x1c -#define GPP_G5_IRQ 0x1d -#define GPP_G6_IRQ 0x1e -#define GPP_G7_IRQ 0x1f +#define GPP_G0_IRQ 0x58 +#define GPP_G1_IRQ 0x59 +#define GPP_G2_IRQ 0x5A +#define GPP_G3_IRQ 0x5B +#define GPP_G4_IRQ 0x5C +#define GPP_G5_IRQ 0x5D +#define GPP_G6_IRQ 0x5E +#define GPP_G7_IRQ 0x5F +#define GPP_G8_IRQ 0x60 +#define GPP_G9_IRQ 0x61 +#define GPP_G10_IRQ 0x62 +#define GPP_G11_IRQ 0x63 +#define GPP_G12_IRQ 0x64 +#define GPP_G13_IRQ 0x65 +#define GPP_G14_IRQ 0x66 +#define GPP_G15_IRQ 0x67 +#define GPP_G16_IRQ 0x68 +#define GPP_G17_IRQ 0x69 +#define GPP_G18_IRQ 0x6A +#define GPP_G19_IRQ 0x6B +#define GPP_G20_IRQ 0x6C +#define GPP_G21_IRQ 0x6D +#define GPP_G22_IRQ 0x6E +#define GPP_G23_IRQ 0x6F -/* Group B */ -#define GPP_B0_IRQ 0x20 -#define GPP_B1_IRQ 0x21 -#define GPP_B2_IRQ 0x22 -#define GPP_B3_IRQ 0x23 -#define GPP_B4_IRQ 0x24 -#define GPP_B5_IRQ 0x25 -#define GPP_B6_IRQ 0x26 -#define GPP_B7_IRQ 0x27 -#define GPP_B8_IRQ 0x28 -#define GPP_B9_IRQ 0x29 -#define GPP_B10_IRQ 0x2a -#define GPP_B11_IRQ 0x2b -#define GPP_B12_IRQ 0x2c -#define GPP_B13_IRQ 0x2d -#define GPP_B14_IRQ 0x2e -#define GPP_B15_IRQ 0x2f -#define GPP_B16_IRQ 0x30 -#define GPP_B17_IRQ 0x31 -#define GPP_B18_IRQ 0x32 -#define GPP_B19_IRQ 0x33 -#define GPP_B20_IRQ 0x34 -#define GPP_B21_IRQ 0x35 -#define GPP_B22_IRQ 0x36 -#define GPP_B23_IRQ 0x37 +/* Group R*/ +#define GPP_R0_IRQ 0x70 +#define GPP_R1_IRQ 0x71 +#define GPP_R2_IRQ 0x72 +#define GPP_R3_IRQ 0x73 +#define GPP_R4_IRQ 0x74 +#define GPP_R5_IRQ 0x75 +#define GPP_R6_IRQ 0x76 +#define GPP_R7_IRQ 0x77 -/* Group A */ -#define GPP_A0_IRQ 0x38 -#define GPP_A1_IRQ 0x39 -#define GPP_A2_IRQ 0x3a -#define GPP_A3_IRQ 0x3b -#define GPP_A4_IRQ 0x3c -#define GPP_A5_IRQ 0x3d -#define GPP_A6_IRQ 0x3e -#define GPP_A7_IRQ 0x3f -#define GPP_A8_IRQ 0x40 -#define GPP_A9_IRQ 0x41 -#define GPP_A10_IRQ 0x42 -#define GPP_A11_IRQ 0x43 -#define GPP_A12_IRQ 0x44 -#define GPP_A13_IRQ 0x45 -#define GPP_A14_IRQ 0x46 -#define GPP_A15_IRQ 0x47 -#define GPP_A16_IRQ 0x48 -#define GPP_A17_IRQ 0x49 -#define GPP_A18_IRQ 0x4a -#define GPP_A19_IRQ 0x4b +/* Group GPD */ +#define GPD0_IRQ 0x21 +#define GPD1_IRQ 0x22 +#define GPD2_IRQ 0x23 +#define GPD3_IRQ 0x24 +#define GPD4_IRQ 0x25 +#define GPD5_IRQ 0x26 +#define GPD6_IRQ 0x27 +#define GPD7_IRQ 0x28 +#define GPD8_IRQ 0x29 +#define GPD9_IRQ 0x2A +#define GPD10_IRQ 0x2B +#define GPD11_IRQ 0x6B + +/* Group V */ +#define GPP_V0_IRQ 0x2C +#define GPP_V1_IRQ 0x2D +#define GPP_V2_IRQ 0x2E +#define GPP_V3_IRQ 0x2F +#define GPP_V4_IRQ 0x30 +#define GPP_V5_IRQ 0x31 +#define GPP_V6_IRQ 0x32 +#define GPP_V7_IRQ 0x33 +#define GPP_V8_IRQ 0x34 +#define GPP_V9_IRQ 0x35 +#define GPP_V10_IRQ 0x36 +#define GPP_V11_IRQ 0x37 +#define GPP_V12_IRQ 0x38 +#define GPP_V13_IRQ 0x39 +#define GPP_V14_IRQ 0x3A +#define GPP_V15_IRQ 0x3B /* Group H */ -#define GPP_H0_IRQ 0x70 -#define GPP_H1_IRQ 0x71 -#define GPP_H2_IRQ 0x72 -#define GPP_H3_IRQ 0x73 -#define GPP_H4_IRQ 0x74 -#define GPP_H5_IRQ 0x75 -#define GPP_H6_IRQ 0x76 -#define GPP_H7_IRQ 0x77 -#define GPP_H8_IRQ 0x18 -#define GPP_H9_IRQ 0x19 -#define GPP_H10_IRQ 0x1a -#define GPP_H11_IRQ 0x1b -#define GPP_H12_IRQ 0x1c -#define GPP_H13_IRQ 0x1d -#define GPP_H14_IRQ 0x1e -#define GPP_H15_IRQ 0x1f -#define GPP_H16_IRQ 0x20 -#define GPP_H17_IRQ 0x21 -#define GPP_H18_IRQ 0x22 -#define GPP_H19_IRQ 0x23 -#define GPP_H20_IRQ 0x24 -#define GPP_H21_IRQ 0x25 -#define GPP_H22_IRQ 0x26 -#define GPP_H23_IRQ 0x27 +#define GPP_H0_IRQ 0x3C +#define GPP_H1_IRQ 0x3D +#define GPP_H2_IRQ 0x3E +#define GPP_H3_IRQ 0x3F +#define GPP_H4_IRQ 0x40 +#define GPP_H5_IRQ 0x41 +#define GPP_H6_IRQ 0x42 +#define GPP_H7_IRQ 0x43 +#define GPP_H8_IRQ 0x44 +#define GPP_H9_IRQ 0x45 +#define GPP_H10_IRQ 0x46 +#define GPP_H11_IRQ 0x47 +#define GPP_H12_IRQ 0x48 +#define GPP_H13_IRQ 0x49 +#define GPP_H14_IRQ 0x4A +#define GPP_H15_IRQ 0x4B +#define GPP_H16_IRQ 0x4C +#define GPP_H17_IRQ 0x4D +#define GPP_H18_IRQ 0x4E +#define GPP_H19_IRQ 0x4F +#define GPP_H20_IRQ 0x50 +#define GPP_H21_IRQ 0x51 +#define GPP_H22_IRQ 0x52 +#define GPP_H23_IRQ 0x53 /* Group D */ -#define GPP_D0_IRQ 0x28 -#define GPP_D1_IRQ 0x29 -#define GPP_D2_IRQ 0x2a -#define GPP_D3_IRQ 0x2b -#define GPP_D4_IRQ 0x2c -#define GPP_D5_IRQ 0x2d -#define GPP_D6_IRQ 0x2e -#define GPP_D7_IRQ 0x2f -#define GPP_D8_IRQ 0x30 -#define GPP_D9_IRQ 0x31 -#define GPP_D10_IRQ 0x32 -#define GPP_D11_IRQ 0x33 -#define GPP_D12_IRQ 0x34 -#define GPP_D13_IRQ 0x35 -#define GPP_D14_IRQ 0x36 -#define GPP_D15_IRQ 0x37 -#define GPP_D16_IRQ 0x38 -#define GPP_D17_IRQ 0x39 -#define GPP_D18_IRQ 0x3a -#define GPP_D19_IRQ 0x3b -#define GPP_D20_IRQ 0x3c -#define GPP_D21_IRQ 0x3d -#define GPP_D22_IRQ 0x3e -#define GPP_D23_IRQ 0x3f +#define GPP_D0_IRQ 0x54 +#define GPP_D1_IRQ 0x6E +#define GPP_D2_IRQ 0x6F +#define GPP_D3_IRQ 0x70 +#define GPP_D4_IRQ 0x71 +#define GPP_D5_IRQ 0x72 +#define GPP_D6_IRQ 0x73 +#define GPP_D7_IRQ 0x74 +#define GPP_D8_IRQ 0x75 +#define GPP_D9_IRQ 0x76 +#define GPP_D10_IRQ 0x77 +#define GPP_D11_IRQ 0x18 +#define GPP_D12_IRQ 0x19 +#define GPP_D13_IRQ 0x1A +#define GPP_D14_IRQ 0x1B +#define GPP_D15_IRQ 0x1C +#define GPP_D16_IRQ 0x1D +#define GPP_D17_IRQ 0x1E +#define GPP_D18_IRQ 0x1F +#define GPP_D19_IRQ 0x20 -/* Group GPD */ -#define GPD0_IRQ 0x64 -#define GPD1_IRQ 0x65 -#define GPD2_IRQ 0x66 -#define GPD3_IRQ 0x67 -#define GPD4_IRQ 0x68 -#define GPD5_IRQ 0x69 -#define GPD6_IRQ 0x6a -#define GPD7_IRQ 0x6b -#define GPD8_IRQ 0x6c -#define GPD9_IRQ 0x6d -#define GPD10_IRQ 0x6e +/* Group U */ +#define GPP_U0_IRQ 0x22 +#define GPP_U1_IRQ 0x23 +#define GPP_U2_IRQ 0x24 +#define GPP_U3_IRQ 0x25 +#define GPP_U4_IRQ 0x56 +#define GPP_U5_IRQ 0x57 +#define GPP_U6_IRQ 0x58 +#define GPP_U7_IRQ 0x59 +#define GPP_U8_IRQ 0x5A +#define GPP_U9_IRQ 0x5B +#define GPP_U10_IRQ 0x5C +#define GPP_U11_IRQ 0x5D +#define GPP_U12_IRQ 0x5E +#define GPP_U13_IRQ 0x5F +#define GPP_U14_IRQ 0x60 +#define GPP_U15_IRQ 0x61 +#define GPP_U16_IRQ 0x62 +#define GPP_U17_IRQ 0x63 +#define GPP_U18_IRQ 0x64 +#define GPP_U19_IRQ 0x65 + +/* Group VGPIO */ +#define VGPIO_4_IRQ 0x6B +#define VGPIO_39_IRQ 0x43 /* Group C */ -#define GPP_C0_IRQ 0x5a -#define GPP_C1_IRQ 0x5b -#define GPP_C2_IRQ 0x5c -#define GPP_C3_IRQ 0x5d -#define GPP_C4_IRQ 0x5e -#define GPP_C5_IRQ 0x5f -#define GPP_C6_IRQ 0x60 -#define GPP_C7_IRQ 0x61 -#define GPP_C8_IRQ 0x62 -#define GPP_C9_IRQ 0x63 -#define GPP_C10_IRQ 0x64 -#define GPP_C11_IRQ 0x65 -#define GPP_C12_IRQ 0x66 -#define GPP_C13_IRQ 0x67 -#define GPP_C14_IRQ 0x68 -#define GPP_C15_IRQ 0x69 -#define GPP_C16_IRQ 0x6a -#define GPP_C17_IRQ 0x6b -#define GPP_C18_IRQ 0x6c -#define GPP_C19_IRQ 0x6d -#define GPP_C20_IRQ 0x6e -#define GPP_C21_IRQ 0x6f -#define GPP_C22_IRQ 0x70 -#define GPP_C23_IRQ 0x71 -/* Group E */ -#define GPP_E0_IRQ 0x72 -#define GPP_E1_IRQ 0x73 -#define GPP_E2_IRQ 0x74 -#define GPP_E3_IRQ 0x75 -#define GPP_E4_IRQ 0x76 -#define GPP_E5_IRQ 0x77 -#define GPP_E6_IRQ 0x18 -#define GPP_E7_IRQ 0x19 -#define GPP_E8_IRQ 0x1a -#define GPP_E9_IRQ 0x1b -#define GPP_E10_IRQ 0x1c -#define GPP_E11_IRQ 0x1d -#define GPP_E12_IRQ 0x1e -#define GPP_E13_IRQ 0x1f -#define GPP_E14_IRQ 0x20 -#define GPP_E15_IRQ 0x21 -#define GPP_E16_IRQ 0x22 -#define GPP_E17_IRQ 0x23 -#define GPP_E18_IRQ 0x24 -#define GPP_E19_IRQ 0x25 -#define GPP_E20_IRQ 0x26 -#define GPP_E21_IRQ 0x27 -#define GPP_E22_IRQ 0x28 -#define GPP_E23_IRQ 0x29 +#define GPP_C0_IRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 -/* Group R*/ -#define GPP_R0_IRQ 0x50 -#define GPP_R1_IRQ 0x51 -#define GPP_R2_IRQ 0x52 -#define GPP_R3_IRQ 0x53 -#define GPP_R4_IRQ 0x54 -#define GPP_R5_IRQ 0x55 -#define GPP_R6_IRQ 0x56 -#define GPP_R7_IRQ 0x57 +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 -/* Group S */ -#define GPP_S0_IRQ 0x5c -#define GPP_S1_IRQ 0x5d -#define GPP_S2_IRQ 0x5e -#define GPP_S3_IRQ 0x5f -#define GPP_S4_IRQ 0x60 -#define GPP_S5_IRQ 0x61 -#define GPP_S6_IRQ 0x62 -#define GPP_S7_IRQ 0x63 +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 /* Register defines. */ #define GPIO_MISCCFG 0x10 #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xc0 +#define HOSTSW_OWN_REG_0 0xb0 #define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1a0 -#define PAD_CFG_BASE 0x600 +#define PAD_CFG_BASE 0x700 #endif diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h index 38e8a7e94b..5d66170f17 100644 --- a/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h @@ -8,339 +8,425 @@ * The GPIO groups are accessed through register blocks called * communities. */ - -#define GPP_A 0x0 -#define GPP_B 0x1 -#define GPP_G 0x2 -#define GPP_C 0x3 +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_D 0x2 +#define GPP_A 0x3 #define GPP_R 0x4 -#define GPP_D 0x5 -#define GPP_S 0x6 +#define GPP_V 0x5 +#define GPD 0x6 #define GPP_H 0x7 -#define GPP_VGPIO 0x8 -#define GPP_F 0x9 -#define GPP_GPD 0xA -#define GPP_E 0xD +#define GPP_U 0x8 +#define VGPIO 0x9 +#define GPP_F 0xA +#define GPP_C 0xB +#define GPP_E 0xC +#define GPP_G 0xD +#define GPP_S 0xE -#define GPIO_MAX_NUM_PER_GROUP 24 -#define SD_PWR_EN_PIN GPP_H1 +#define GPIO_NUM_GROUPS 15 +#define GPIO_MAX_NUM_PER_GROUP 32 +#define SD_PWR_EN_PIN GPP_H17 /* * GPIOs are ordered monotonically increasing to match ACPI/OS driver. */ -/* Group F */ -#define GPP_F0 0 -#define GPP_F1 1 -#define GPP_F2 2 -#define GPP_F3 3 -#define GPP_F4 4 -#define GPP_F5 5 -#define GPP_F6 6 -#define GPP_F7 7 -#define GPP_F8 8 -#define GPP_F9 9 -#define GPP_F10 10 -#define GPP_F11 11 -#define GPP_F12 12 -#define GPP_F13 13 -#define GPP_F14 14 -#define GPP_F15 15 -#define GPP_F16 16 -#define GPP_F17 17 -#define GPP_F18 18 -#define GPP_F19 19 - /* Group B */ -#define GPIO_RSVD_0 20 -#define GPIO_RSVD_1 21 -#define GPIO_RSVD_2 22 -#define GPIO_RSVD_3 23 -#define GPIO_RSVD_4 24 -#define GPIO_RSVD_5 25 -#define GPIO_RSVD_6 26 -#define GPIO_RSVD_7 27 -#define GPIO_RSVD_8 28 -#define GPP_B0 29 -#define GPP_B1 30 -#define GPP_B2 31 -#define GPP_B3 32 -#define GPP_B4 33 -#define GPP_B5 34 -#define GPP_B6 35 -#define GPP_B7 36 -#define GPP_B8 37 -#define GPP_B9 38 -#define GPP_B10 39 -#define GPP_B11 40 -#define GPP_B12 41 -#define GPP_B13 42 -#define GPP_B14 43 -#define GPP_B15 44 -#define GPP_B16 45 -#define GPP_B17 46 -#define GPP_B18 47 -#define GPP_B19 48 -#define GPP_B20 49 -#define GPP_B21 50 -#define GPP_B22 51 -#define GPP_B23 52 -#define GPIO_RSVD_9 53 -#define GPIO_RSVD_10 54 +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPIO_RSVD_0 24 +#define GPIO_RSVD_1 25 -/* Group A */ -#define GPP_A0 55 -#define GPP_A1 56 -#define GPP_A2 57 -#define GPP_A3 58 -#define GPP_A4 59 -#define GPP_A5 60 -#define GPP_A6 61 -#define GPP_A7 62 -#define GPP_A8 63 -#define GPP_A9 64 -#define GPP_A10 65 -#define GPP_A11 66 -#define GPP_A12 67 -#define GPP_A13 68 -#define GPP_A14 69 -#define GPP_A15 70 -#define GPP_A16 71 -#define GPP_A17 72 -#define GPP_A18 73 -#define GPP_A19 74 -#define GPIO_RSVD_11 75 - -/* Group S */ -#define GPP_S0 76 -#define GPP_S1 77 -#define GPP_S2 78 -#define GPP_S3 79 -#define GPP_S4 80 -#define GPP_S5 81 -#define GPP_S6 82 -#define GPP_S7 83 +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 -/* Group R */ -#define GPP_R0 84 -#define GPP_R1 85 -#define GPP_R2 86 -#define GPP_R3 87 -#define GPP_R4 88 -#define GPP_R5 89 -#define GPP_R6 90 -#define GPP_R7 91 +/* Group G */ +#define GPP_G0 42 +#define GPP_G1 43 +#define GPP_G2 44 +#define GPP_G3 45 +#define GPP_G4 46 +#define GPP_G5 47 +#define GPP_G6 48 +#define GPP_G7 49 +#define GPP_G8 50 +#define GPP_G9 51 +#define GPP_G10 52 +#define GPP_G11 53 +#define GPP_G12 54 +#define GPP_G13 55 +#define GPP_G14 56 +#define GPP_G15 57 +#define GPP_G16 58 +#define GPP_G17 59 +#define GPP_G18 60 +#define GPP_G19 61 +#define GPP_G20 62 +#define GPP_G21 63 +#define GPP_G22 64 +#define GPP_G23 65 +#define GPIO_RSVD_2 66 -#define GPIO_COM0_START GPP_F0 -#define GPIO_COM0_END GPP_R7 +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPIO_RSVD_2 #define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) +/* Group V */ +#define GPP_V0 67 +#define GPP_V1 68 +#define GPP_V2 69 +#define GPP_V3 70 +#define GPP_V4 71 +#define GPP_V5 72 +#define GPP_V6 73 +#define GPP_V7 74 +#define GPP_V8 75 +#define GPP_V9 76 +#define GPP_V10 77 +#define GPP_V11 78 +#define GPP_V12 79 +#define GPP_V13 80 +#define GPP_V14 81 +#define GPP_V15 82 + /* Group H */ -#define GPP_H0 92 -#define GPP_H1 93 -#define GPP_H2 94 -#define GPP_H3 95 -#define GPP_H4 96 -#define GPP_H5 97 -#define GPP_H6 98 -#define GPP_H7 99 -#define GPP_H8 100 -#define GPP_H9 101 -#define GPP_H10 102 -#define GPP_H11 103 -#define GPP_H12 104 -#define GPP_H13 105 -#define GPP_H14 106 -#define GPP_H15 107 -#define GPP_H16 108 -#define GPP_H17 109 -#define GPP_H18 110 -#define GPP_H19 111 -#define GPP_H20 112 -#define GPP_H21 113 -#define GPP_H22 114 -#define GPP_H23 115 +#define GPP_H0 83 +#define GPP_H1 84 +#define GPP_H2 85 +#define GPP_H3 86 +#define GPP_H4 87 +#define GPP_H5 88 +#define GPP_H6 89 +#define GPP_H7 90 +#define GPP_H8 91 +#define GPP_H9 92 +#define GPP_H10 93 +#define GPP_H11 94 +#define GPP_H12 95 +#define GPP_H13 96 +#define GPP_H14 97 +#define GPP_H15 98 +#define GPP_H16 99 +#define GPP_H17 100 +#define GPP_H18 101 +#define GPP_H19 102 +#define GPP_H20 103 +#define GPP_H21 104 +#define GPP_H22 105 +#define GPP_H23 106 /* Group D */ -#define GPP_D0 116 -#define GPP_D1 117 -#define GPP_D2 118 -#define GPP_D3 119 -#define GPP_D4 120 -#define GPP_D5 121 -#define GPP_D6 122 -#define GPP_D7 123 -#define GPP_D8 124 -#define GPP_D9 125 -#define GPP_D10 126 -#define GPP_D11 127 -#define GPP_D12 128 -#define GPP_D13 129 -#define GPP_D14 130 -#define GPP_D15 131 -#define GPP_D16 132 -#define GPP_D17 133 -#define GPP_D18 134 -#define GPP_D19 135 -#define GPP_D20 136 -#define GPP_D21 137 -#define GPP_D22 138 -#define GPP_D23 139 -#define GPIO_RSVD_12 140 -#define GPIO_RSVD_13 141 +#define GPP_D0 107 +#define GPP_D1 108 +#define GPP_D2 109 +#define GPP_D3 110 +#define GPP_D4 111 +#define GPP_D5 112 +#define GPP_D6 113 +#define GPP_D7 114 +#define GPP_D8 115 +#define GPP_D9 116 +#define GPP_D10 117 +#define GPP_D11 118 +#define GPP_D12 119 +#define GPP_D13 120 +#define GPP_D14 121 +#define GPP_D15 122 +#define GPP_D16 123 +#define GPP_D17 124 +#define GPP_D18 125 +#define GPP_D19 126 +#define GPIO_RSVD_3 127 -/* Group VGPIO */ -#define VGPIO_0 142 -#define VGPIO_3 143 -#define VGPIO_4 144 -#define VGPIO_5 145 -#define VGPIO_6 146 -#define VGPIO_7 147 -#define VGPIO_8 148 -#define VGPIO_9 149 -#define VGPIO_10 150 -#define VGPIO_11 151 -#define VGPIO_12 152 -#define VGPIO_13 153 -#define VGPIO_18 154 -#define VGPIO_19 155 -#define VGPIO_20 156 -#define VGPIO_21 157 -#define VGPIO_22 158 -#define VGPIO_23 159 -#define VGPIO_24 160 -#define VGPIO_25 161 -#define VGPIO_30 162 -#define VGPIO_31 163 -#define VGPIO_32 164 -#define VGPIO_33 165 -#define VGPIO_34 166 -#define VGPIO_35 167 -#define VGPIO_36 168 -#define VGPIO_37 169 -#define VGPIO_39 170 +/* Group U */ +#define GPP_U0 128 +#define GPP_U1 129 +#define GPP_U2 130 +#define GPP_U3 131 +#define GPP_U4 132 +#define GPP_U5 133 +#define GPP_U6 134 +#define GPP_U7 135 +#define GPP_U8 136 +#define GPP_U9 137 +#define GPP_U10 138 +#define GPP_U11 139 +#define GPP_U12 140 +#define GPP_U13 141 +#define GPP_U14 142 +#define GPP_U15 143 +#define GPP_U16 144 +#define GPP_U17 145 +#define GPP_U18 146 +#define GPP_U19 147 +#define GPIO_RSVD_4 148 +#define GPIO_RSVD_5 149 +#define GPIO_RSVD_6 150 +#define GPIO_RSVD_7 151 -/* Group C */ -#define GPP_C0 171 -#define GPP_C1 172 -#define GPP_C2 173 -#define GPP_C3 174 -#define GPP_C4 175 -#define GPP_C5 176 -#define GPP_C6 177 -#define GPP_C7 178 -#define GPP_C8 179 -#define GPP_C9 180 -#define GPP_C10 181 -#define GPP_C11 182 -#define GPP_C12 183 -#define GPP_C13 184 -#define GPP_C14 185 -#define GPP_C15 186 -#define GPP_C16 187 -#define GPP_C17 188 -#define GPP_C18 189 -#define GPP_C19 190 -#define GPP_C20 191 -#define GPP_C21 192 -#define GPP_C22 193 -#define GPP_C23 194 +/* Group VGPIO */ +#define VGPIO_0 152 +#define VGPIO_4 153 +#define VGPIO_5 154 +#define VGPIO_6 155 +#define VGPIO_7 156 +#define VGPIO_8 157 +#define VGPIO_9 158 +#define VGPIO_10 159 +#define VGPIO_11 160 +#define VGPIO_12 161 +#define VGPIO_13 162 +#define VGPIO_18 163 +#define VGPIO_19 164 +#define VGPIO_20 165 +#define VGPIO_21 166 +#define VGPIO_22 167 +#define VGPIO_23 168 +#define VGPIO_24 169 +#define VGPIO_25 170 +#define VGPIO_30 171 +#define VGPIO_31 172 +#define VGPIO_32 173 +#define VGPIO_33 174 +#define VGPIO_34 175 +#define VGPIO_35 176 +#define VGPIO_36 177 +#define VGPIO_37 178 +#define VGPIO_39 179 -#define GPIO_COM1_START GPP_H0 -#define GPIO_COM1_END GPP_C23 +#define GPIO_COM1_START GPP_V0 +#define GPIO_COM1_END VGPIO_39 #define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) -/* Group GPD */ -#define GPD0 195 -#define GPD1 196 -#define GPD2 197 -#define GPD3 198 -#define GPD4 199 -#define GPD5 200 -#define GPD6 201 -#define GPD7 202 -#define GPD8 203 -#define GPD9 204 -#define GPD10 205 -#define GPIO_RSVD_14 206 -#define GPIO_RSVD_15 207 -#define GPIO_RSVD_16 208 -#define GPIO_RSVD_17 209 +/* Group GPD */ +#define GPD0 180 +#define GPD1 181 +#define GPD2 182 +#define GPD3 183 +#define GPD4 184 +#define GPD5 185 +#define GPD6 186 +#define GPD7 187 +#define GPD8 188 +#define GPD9 189 +#define GPD10 190 +#define GPD11 191 +#define GPIO_RSVD_8 192 +#define GPIO_RSVD_9 193 +#define GPIO_RSVD_10 194 +#define GPIO_RSVD_11 195 +#define GPIO_RSVD_12 196 #define GPIO_COM2_START GPD0 -#define GPIO_COM2_END GPIO_RSVD_17 +#define GPIO_COM2_END GPIO_RSVD_2 #define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) +/* Group S */ +#define GPIO_RSVD_13 197 +#define GPIO_RSVD_14 198 +#define GPIO_RSVD_15 199 +#define GPIO_RSVD_16 200 +#define GPIO_RSVD_17 201 +#define GPIO_RSVD_18 202 +#define GPIO_RSVD_19 203 +#define GPIO_RSVD_20 204 +#define GPIO_RSVD_21 205 +#define GPIO_RSVD_22 206 +#define GPIO_RSVD_23 207 +#define GPIO_RSVD_24 208 +#define GPIO_RSVD_25 209 +#define GPIO_RSVD_26 210 +#define GPIO_RSVD_27 211 +#define GPIO_RSVD_28 212 +#define GPIO_RSVD_29 213 +#define GPP_S0 214 +#define GPP_S1 215 + +/* Group A */ +#define GPP_A0 216 +#define GPP_A1 217 +#define GPP_A2 218 +#define GPP_A3 219 +#define GPP_A4 220 +#define GPP_A5 221 +#define GPP_A6 222 +#define GPP_A7 223 +#define GPP_A8 224 +#define GPP_A9 225 +#define GPP_A10 226 +#define GPP_A11 227 +#define GPP_A12 228 +#define GPP_A13 229 +#define GPP_A14 230 +#define GPP_A15 231 +#define GPP_A16 232 +#define GPP_A17 233 +#define GPP_A18 234 +#define GPP_A19 235 +#define GPP_A20 236 +#define GPP_A21 237 +#define GPP_A22 238 +#define GPP_A23 239 + +/* Group VGPIO 3 */ +#define VGPIO_USB_0 240 +#define VGPIO_USB_1 241 +#define VGPIO_USB_2 242 +#define VGPIO_USB_3 243 + +#define GPIO_COM3_START GPIO_RSVD_13 +#define GPIO_COM3_END VGPIO_USB_3 +#define NUM_GPIO_COM3_PADS (GPIO_COM3_END - GPIO_COM3_START + 1) + +/* Group C */ +#define GPP_C0 244 +#define GPP_C1 245 +#define GPP_C2 246 +#define GPP_C3 247 +#define GPP_C4 248 +#define GPP_C5 249 +#define GPP_C6 250 +#define GPP_C7 251 +#define GPP_C8 252 +#define GPP_C9 253 +#define GPP_C10 254 +#define GPP_C11 255 +#define GPP_C12 256 +#define GPP_C13 257 +#define GPP_C14 258 +#define GPP_C15 259 +#define GPP_C16 260 +#define GPP_C17 261 +#define GPP_C18 262 +#define GPP_C19 263 +#define GPP_C20 264 +#define GPP_C21 265 +#define GPP_C22 266 +#define GPP_C23 267 + +/* Group F */ +#define GPP_F0 268 +#define GPP_F1 269 +#define GPP_F2 270 +#define GPP_F3 271 +#define GPP_F4 272 +#define GPP_F5 273 +#define GPP_F6 274 +#define GPP_F7 275 +#define GPP_F8 276 +#define GPP_F9 277 +#define GPP_F10 278 +#define GPP_F11 279 +#define GPP_F12 280 +#define GPP_F13 281 +#define GPP_F14 282 +#define GPP_F15 283 +#define GPP_F16 284 +#define GPP_F17 285 +#define GPP_F18 286 +#define GPP_F19 287 +#define GPP_F20 288 +#define GPP_F21 289 +#define GPP_F22 290 +#define GPP_F23 291 +#define GPIO_RSVD_30 292 +#define GPIO_RSVD_31 293 +#define GPIO_RSVD_32 294 +#define GPIO_RSVD_33 295 +#define GPIO_RSVD_34 296 +#define GPIO_RSVD_35 297 +#define GPIO_RSVD_36 298 + /* Group E */ -#define GPIO_RSVD_18 210 -#define GPIO_RSVD_19 211 -#define GPIO_RSVD_20 212 -#define GPIO_RSVD_21 213 -#define GPIO_RSVD_22 214 -#define GPIO_RSVD_23 215 -#define GPP_E0 216 -#define GPP_E1 217 -#define GPP_E2 218 -#define GPP_E3 219 -#define GPP_E4 220 -#define GPP_E5 221 -#define GPP_E6 222 -#define GPP_E7 223 -#define GPP_E8 224 -#define GPP_E9 225 -#define GPP_E10 226 -#define GPP_E11 227 -#define GPP_E12 228 -#define GPP_E13 229 -#define GPP_E14 230 -#define GPP_E15 231 -#define GPP_E16 232 -#define GPP_E17 233 -#define GPP_E18 234 -#define GPP_E19 235 -#define GPP_E20 236 -#define GPP_E21 237 -#define GPP_E22 238 -#define GPP_E23 239 -#define GPIO_RSVD_24 240 -#define GPIO_RSVD_25 241 -#define GPIO_RSVD_26 242 -#define GPIO_RSVD_27 243 -#define GPIO_RSVD_28 244 -#define GPIO_RSVD_29 245 -#define GPIO_RSVD_30 246 -#define GPIO_RSVD_31 247 -#define GPIO_RSVD_32 248 -#define GPIO_RSVD_33 249 -#define GPIO_RSVD_34 250 -#define GPIO_RSVD_35 251 -#define GPIO_RSVD_36 252 +#define GPP_E0 299 +#define GPP_E1 300 +#define GPP_E2 301 +#define GPP_E3 302 +#define GPP_E4 303 +#define GPP_E5 304 +#define GPP_E6 305 +#define GPP_E7 306 +#define GPP_E8 307 +#define GPP_E9 308 +#define GPP_E10 309 +#define GPP_E11 310 +#define GPP_E12 311 +#define GPP_E13 312 +#define GPP_E14 313 +#define GPP_E15 314 +#define GPP_E16 315 +#define GPP_E17 316 +#define GPP_E18 317 +#define GPP_E19 318 +#define GPP_E20 319 +#define GPP_E21 320 +#define GPP_E22 321 +#define GPP_E23 322 -#define GPIO_COM4_START GPIO_RSVD_18 -#define GPIO_COM4_END GPIO_RSVD_36 +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_E23 #define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) -/* Group G */ -#define GPP_G0 253 -#define GPP_G1 254 -#define GPP_G2 255 -#define GPP_G3 256 -#define GPP_G4 257 -#define GPP_G5 258 -#define GPP_G6 259 -#define GPP_G7 260 +/* Group R */ +#define GPP_R0 323 +#define GPP_R1 324 +#define GPP_R2 325 +#define GPP_R3 326 +#define GPP_R4 327 +#define GPP_R5 328 +#define GPP_R6 329 +#define GPP_R7 330 -#define GPIO_COM5_START GPP_G0 -#define GPIO_COM5_END GPP_G7 +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_R7 #define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) -#define TOTAL_PADS 261 +#define TOTAL_PADS 331 -#define COMM_0 0 -#define COMM_1 1 -#define COMM_2 2 -#define COMM_4 3 -#define COMM_5 4 -#define TOTAL_GPIO_COMM 5 +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_3 3 +#define COMM_4 4 +#define COMM_5 5 +#define TOTAL_GPIO_COMM 6 #endif diff --git a/src/soc/intel/elkhartlake/include/soc/pcr_ids.h b/src/soc/intel/elkhartlake/include/soc/pcr_ids.h index c5c5b31ca2..dbb886895f 100644 --- a/src/soc/intel/elkhartlake/include/soc/pcr_ids.h +++ b/src/soc/intel/elkhartlake/include/soc/pcr_ids.h @@ -11,6 +11,7 @@ #define PID_GPIOCOM0 0x6e #define PID_GPIOCOM1 0x6d #define PID_GPIOCOM2 0x6c +#define PID_GPIOCOM3 0x6b #define PID_GPIOCOM4 0x6a #define PID_GPIOCOM5 0x69 |