diff options
| -rw-r--r-- | src/mainboard/asus/p2b-ds/romstage.c | 11 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b-ls/romstage.c | 11 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b/romstage.c | 11 | ||||
| -rw-r--r-- | src/mainboard/asus/p3b-f/romstage.c | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/i440bx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/i440bx/raminit.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/i440bx/raminit.h | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/i440bx/romstage.c | 30 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/early_smbus.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 1 |
10 files changed, 46 insertions, 52 deletions
diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 36f45a0d0a..d0456e5296 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -14,22 +14,13 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> -#include <cbmem.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_romstage_entry(void) +void mainboard_enable_serial(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - sdram_initialize(); - cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 87cb7531c7..b79ac82918 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -14,23 +14,14 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> -#include <cbmem.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_romstage_entry(void) +void mainboard_enable_serial(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - sdram_initialize(); - cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 8cbc59646d..fbd7124105 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -14,22 +14,13 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> -#include <cbmem.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_romstage_entry(void) +void mainboard_enable_serial(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - sdram_initialize(); - cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e9c41b1a95..209dd96c50 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -15,14 +15,11 @@ */ #include <arch/io.h> -#include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> -#include <cbmem.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -58,16 +55,7 @@ void disable_spd(void) outb(0x67, PM_IO_BASE + 0x37); } -void mainboard_romstage_entry(void) +void mainboard_enable_serial(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - enable_pm(); - - - sdram_initialize(); - - cbmem_initialize_empty(); } diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 355d9b2524..57025859d3 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -19,6 +19,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) ramstage-y += northbridge.c romstage-y += raminit.c +romstage-y += romstage.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c romstage-y += memmap.c diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 08019880b7..597ba946b4 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -667,7 +667,7 @@ static void spd_enable_refresh(void) Public interface. -----------------------------------------------------------------------------*/ -void sdram_set_registers(void) +static void sdram_set_registers(void) { int i, max; uint8_t reg; @@ -977,7 +977,7 @@ static void set_dram_row_attributes(void) PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value); } -void sdram_set_spd_registers(void) +static void sdram_set_spd_registers(void) { /* Setup DRAM row boundary registers and other attributes. */ set_dram_row_attributes(); @@ -993,7 +993,7 @@ void sdram_set_spd_registers(void) pci_write_config8(NB, DRAMT, 0x03); } -void sdram_enable(void) +static void sdram_enable(void) { int i; diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 347c1fecd7..1e9f25b8be 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -22,13 +22,8 @@ void enable_spd(void); void disable_spd(void); - -/* Function prototypes. */ -void sdram_set_registers(void); -void sdram_set_spd_registers(void); -void sdram_enable(void); -/* A merger of above functions */ void sdram_initialize(void); +void mainboard_enable_serial(void); /* Debug */ #if CONFIG(DEBUG_RAM_SETUP) diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c new file mode 100644 index 0000000000..1dee03a984 --- /dev/null +++ b/src/northbridge/intel/i440bx/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> + +void mainboard_romstage_entry(void) +{ + mainboard_enable_serial(); + console_init(); + + i82371eb_early_init(); + + sdram_initialize(); + cbmem_initialize_empty(); +} diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 917a3b45f1..f69cb93a74 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -23,6 +23,12 @@ #include <device/smbus_host.h> #include "i82371eb.h" +void i82371eb_early_init(void) +{ + enable_smbus(); + enable_pm(); +} + void enable_smbus(void) { pci_devfn_t dev; diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 55242effca..b292beb173 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,6 +21,7 @@ void enable_smbus(void); void enable_pm(void); +void i82371eb_early_init(void); #if ENV_ROMSTAGE int smbus_read_byte(u8 device, u8 address); |