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-rw-r--r--src/device/Kconfig8
-rw-r--r--src/mainboard/emulation/qemu-q35/Kconfig1
-rw-r--r--src/northbridge/amd/agesa/family14/Kconfig2
-rw-r--r--src/northbridge/amd/agesa/family15tn/Kconfig2
-rw-r--r--src/northbridge/amd/agesa/family16kb/Kconfig2
-rw-r--r--src/northbridge/amd/pi/00630F01/Kconfig2
-rw-r--r--src/northbridge/amd/pi/00730F01/Kconfig2
-rw-r--r--src/northbridge/intel/gm45/Kconfig1
-rw-r--r--src/northbridge/intel/haswell/Kconfig1
-rw-r--r--src/northbridge/intel/i945/Kconfig1
-rw-r--r--src/northbridge/intel/ironlake/Kconfig2
-rw-r--r--src/northbridge/intel/pineview/Kconfig1
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig1
-rw-r--r--src/northbridge/intel/x4x/Kconfig1
-rw-r--r--src/soc/amd/cezanne/Kconfig2
-rw-r--r--src/soc/amd/picasso/Kconfig2
-rw-r--r--src/soc/amd/stoneyridge/Kconfig2
-rw-r--r--src/soc/intel/alderlake/Kconfig1
-rw-r--r--src/soc/intel/baytrail/Kconfig1
-rw-r--r--src/soc/intel/braswell/Kconfig1
-rw-r--r--src/soc/intel/common/block/systemagent/Kconfig1
-rw-r--r--src/soc/intel/denverton_ns/Kconfig1
-rw-r--r--src/soc/intel/elkhartlake/Kconfig1
-rw-r--r--src/soc/intel/icelake/Kconfig1
-rw-r--r--src/soc/intel/jasperlake/Kconfig1
-rw-r--r--src/soc/intel/tigerlake/Kconfig1
-rw-r--r--src/soc/intel/xeon_sp/Kconfig1
27 files changed, 8 insertions, 35 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig
index bb4e913f35..52102230a3 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -513,6 +513,14 @@ config PCIEXP_PLUGIN_SUPPORT
bool
default y
+config MMCONF_BASE_ADDRESS
+ hex
+ depends on MMCONF_SUPPORT
+
+config MMCONF_BUS_NUMBER
+ int
+ depends on MMCONF_SUPPORT
+
config PCI_ALLOW_BUS_MASTER
bool "Allow coreboot to set optional PCI bus master bits"
default y
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index 5a77ded9b3..9958cafc92 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -61,7 +61,6 @@ config MAINBOARD_PART_NUMBER
default "QEMU x86 q35/ich9"
config MMCONF_BASE_ADDRESS
- hex
default 0xb0000000
# fw_cfg tables can be larger than the default when TPM is enabled
diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig
index edd7dcb3ad..9c7eb9236c 100644
--- a/src/northbridge/amd/agesa/family14/Kconfig
+++ b/src/northbridge/amd/agesa/family14/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
default 0x100000
config MMCONF_BASE_ADDRESS
- hex
default 0xF8000000
config MMCONF_BUS_NUMBER
- int
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY14
diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig
index 8f012d5083..60007a32ce 100644
--- a/src/northbridge/amd/agesa/family15tn/Kconfig
+++ b/src/northbridge/amd/agesa/family15tn/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
default 0x100000
config MMCONF_BASE_ADDRESS
- hex
default 0xF8000000
config MMCONF_BUS_NUMBER
- int
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig
index 4488f8dc42..d1ccbb51ac 100644
--- a/src/northbridge/amd/agesa/family16kb/Kconfig
+++ b/src/northbridge/amd/agesa/family16kb/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
default 0x100000
config MMCONF_BASE_ADDRESS
- hex
default 0xF8000000
config MMCONF_BUS_NUMBER
- int
default 64
config VGA_BIOS_ID
diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig
index 292492e6ea..c61d39dc13 100644
--- a/src/northbridge/amd/pi/00630F01/Kconfig
+++ b/src/northbridge/amd/pi/00630F01/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
default 0x100000
config MMCONF_BASE_ADDRESS
- hex
default 0xF8000000
config MMCONF_BUS_NUMBER
- int
default 64
config VGA_BIOS_ID
diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig
index cb655062d0..0aaaf49cab 100644
--- a/src/northbridge/amd/pi/00730F01/Kconfig
+++ b/src/northbridge/amd/pi/00730F01/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
default 0x100000
config MMCONF_BASE_ADDRESS
- hex
default 0xF8000000
config MMCONF_BUS_NUMBER
- int
default 64
config VGA_BIOS_ID
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index f5d6712386..4637a22561 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -27,7 +27,6 @@ config VGA_BIOS_ID
default "8086,2a42"
config MMCONF_BASE_ADDRESS
- hex
default 0xf0000000
config SMM_RESERVED_SIZE
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 04ab373ce2..5801658aa2 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -34,7 +34,6 @@ config VGA_BIOS_ID
default "8086,0166"
config MMCONF_BASE_ADDRESS
- hex
default 0xf0000000
config DCACHE_RAM_BASE
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index d6498f1e81..7fc3e28001 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -39,7 +39,6 @@ config I945_LVDS
LVDS.
config MMCONF_BASE_ADDRESS
- hex
default 0xf0000000
config OVERRIDE_CLOCK_DISABLE
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index fbad4be671..d371dac729 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -19,7 +19,6 @@ config VBOOT
select TPM_STARTUP_IGNORE_POSTINIT
config MMCONF_BUS_NUMBER
- int
default 256
config CBFS_SIZE
@@ -46,7 +45,6 @@ config DCACHE_BSP_STACK_SIZE
other stages.
config MMCONF_BASE_ADDRESS
- hex
default 0xe0000000
config INTEL_GMA_BCLV_OFFSET
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 185beebedf..535e8e2720 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -21,7 +21,6 @@ config VGA_BIOS_ID
default "8086,a001"
config MMCONF_BASE_ADDRESS
- hex
default 0xe0000000
config SMM_RESERVED_SIZE
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 1388b8770d..0ec4ba2971 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -86,7 +86,6 @@ config VGA_BIOS_ID
default "8086,0106"
config MMCONF_BASE_ADDRESS
- hex
default 0xf0000000
help
The MRC blob requires it to be at 0xf0000000.
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 00e9a3ad21..bdef6f2132 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -23,7 +23,6 @@ config VGA_BIOS_ID
default "8086,2e32"
config MMCONF_BASE_ADDRESS
- hex
default 0xe0000000
config SMM_RESERVED_SIZE
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index d405cdde5b..d8f994e231 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -114,11 +114,9 @@ config CPU_ADDR_BITS
default 48
config MMCONF_BASE_ADDRESS
- hex
default 0xF8000000
config MMCONF_BUS_NUMBER
- int
default 64
config MAX_CPUS
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 48132fcfa1..4989ee2412 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -180,11 +180,9 @@ config CPU_ADDR_BITS
default 48
config MMCONF_BASE_ADDRESS
- hex
default 0xF8000000
config MMCONF_BUS_NUMBER
- int
default 64
config VERSTAGE_ADDR
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 6aebd85e1d..baf3f4e9df 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -125,11 +125,9 @@ config BOTTOMIO_POSITION
ranges are present.
config MMCONF_BASE_ADDRESS
- hex
default 0xF8000000
config MMCONF_BUS_NUMBER
- int
default 64
config VGA_BIOS_ID
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index c67c424b2c..7289e02032 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -159,7 +159,6 @@ config PCR_BASE_ADDRESS
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
- hex
default 0xc0000000
config CPU_BCLK_MHZ
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 33923d0dc0..6d91d5850e 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -42,7 +42,6 @@ config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config MMCONF_BASE_ADDRESS
- hex
default 0xe0000000
config MAX_CPUS
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index c2522b2be7..fcf07fafab 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -57,7 +57,6 @@ config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config MMCONF_BASE_ADDRESS
- hex
default 0xe0000000
config MAX_CPUS
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
index 6dd1f3b363..c8aecabaad 100644
--- a/src/soc/intel/common/block/systemagent/Kconfig
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -6,7 +6,6 @@ config SOC_INTEL_COMMON_BLOCK_SA
if SOC_INTEL_COMMON_BLOCK_SA
config MMCONF_BASE_ADDRESS
- hex
default 0xe0000000
config SA_PCIEX_LENGTH
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index a7af6d587b..aa5c3456d6 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -44,7 +44,6 @@ config CPU_SPECIFIC_OPTIONS
select SUPPORT_CPU_UCODE_IN_CBFS
config MMCONF_BASE_ADDRESS
- hex
default 0xe0000000
config FSP_T_ADDR
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 4e7533583e..24ef8b3efc 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -127,7 +127,6 @@ config PCR_BASE_ADDRESS
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
- hex
default 0xc0000000
config CPU_BCLK_MHZ
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 2fb0e6442f..3d56758ce8 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -123,7 +123,6 @@ config PCR_BASE_ADDRESS
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
- hex
default 0xc0000000
config CPU_BCLK_MHZ
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 2b73aad9c7..5324d84142 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -127,7 +127,6 @@ config PCR_BASE_ADDRESS
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
- hex
default 0xc0000000
config CPU_BCLK_MHZ
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 4962208d3a..cd84bdf453 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -146,7 +146,6 @@ config PCR_BASE_ADDRESS
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
- hex
default 0xc0000000
config CPU_BCLK_MHZ
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 3dfc86fb3c..6c10c35039 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -100,7 +100,6 @@ config DCACHE_BSP_STACK_SIZE
default 0x10000
config MMCONF_BASE_ADDRESS
- hex
default 0x80000000
config HEAP_SIZE