diff options
| -rw-r--r-- | src/mainboard/google/hatch/variants/puff/overridetree.cb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 4ffbfed2b2..cca2d41ce3 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -2,6 +2,9 @@ chip soc/intel/cannonlake # Enable heci communication register "HeciEnabled" = "1" + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -166,6 +169,9 @@ chip soc/intel/cannonlake # PCIe port 7 for LAN register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" @@ -281,6 +287,7 @@ chip soc/intel/cannonlake end end # FSP requires func0 be enabled. device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end |