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-rw-r--r--src/device/dram/Makefile.inc2
-rw-r--r--src/device/dram/ddr4.c78
-rw-r--r--src/include/device/dram/ddr4.h5
-rw-r--r--tests/device/Makefile.inc5
-rw-r--r--tests/device/ddr4-test.c41
5 files changed, 131 insertions, 0 deletions
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index f397a534f2..f7118dbbc2 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1 +1,3 @@
romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c
+
+ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c
diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c
index 429a9d271a..e670b20f72 100644
--- a/src/device/dram/ddr4.c
+++ b/src/device/dram/ddr4.c
@@ -9,6 +9,69 @@
#include <smbios.h>
#include <types.h>
+enum ddr4_speed_grade {
+ DDR4_1600,
+ DDR4_1866,
+ DDR4_2133,
+ DDR4_2400,
+ DDR4_2666,
+ DDR4_2933,
+ DDR4_3200
+};
+
+struct ddr4_speed_attr {
+ uint32_t min_clock_mhz; // inclusive
+ uint32_t max_clock_mhz; // inclusive
+ uint32_t reported_mts;
+};
+
+/**
+ * DDR4 speed attributes derived from JEDEC 79-4C tables 169 & 170
+ *
+ * min_clock_mhz = 1000/max_tCk_avg(ns) + 1
+ * Adding 1 to make minimum inclusive
+ * max_clock_mhz = 1000/min_tCk_avg(ns)
+ * reported_mts = Standard reported DDR4 speed in MT/s
+ * May be 1 less than the actual max MT/s
+ */
+static const struct ddr4_speed_attr ddr4_speeds[] = {
+ [DDR4_1600] = {
+ .min_clock_mhz = 668,
+ .max_clock_mhz = 800,
+ .reported_mts = 1600
+ },
+ [DDR4_1866] = {
+ .min_clock_mhz = 801,
+ .max_clock_mhz = 934,
+ .reported_mts = 1866
+ },
+ [DDR4_2133] = {
+ .min_clock_mhz = 935,
+ .max_clock_mhz = 1067,
+ .reported_mts = 2133
+ },
+ [DDR4_2400] = {
+ .min_clock_mhz = 1068,
+ .max_clock_mhz = 1200,
+ .reported_mts = 2400
+ },
+ [DDR4_2666] = {
+ .min_clock_mhz = 1201,
+ .max_clock_mhz = 1333,
+ .reported_mts = 2666
+ },
+ [DDR4_2933] = {
+ .min_clock_mhz = 1334,
+ .max_clock_mhz = 1466,
+ .reported_mts = 2933
+ },
+ [DDR4_3200] = {
+ .min_clock_mhz = 1467,
+ .max_clock_mhz = 1600,
+ .reported_mts = 3200
+ }
+};
+
typedef enum {
BLOCK_0, /* Base Configuration and DRAM Parameters */
BLOCK_1,
@@ -68,6 +131,21 @@ static bool block_exists(spd_block_type type, u8 dimm_type)
}
}
+/**
+ * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s
+ */
+uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz)
+{
+ for (enum ddr4_speed_grade speed = 0; speed < ARRAY_SIZE(ddr4_speeds); speed++) {
+ const struct ddr4_speed_attr *speed_attr = &ddr4_speeds[speed];
+ if (speed_mhz >= speed_attr->min_clock_mhz &&
+ speed_mhz <= speed_attr->max_clock_mhz) {
+ return speed_attr->reported_mts;
+ }
+ }
+ printk(BIOS_ERR, "ERROR: DDR4 speed of %d MHz is out of range", speed_mhz);
+ return 0;
+}
/**
* \brief Decode the raw SPD data
diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h
index d22d4bc500..eac8bf8920 100644
--- a/src/include/device/dram/ddr4.h
+++ b/src/include/device/dram/ddr4.h
@@ -69,4 +69,9 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot,
const u16 selected_freq,
const dimm_attr *info);
+/**
+ * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s
+ */
+uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz);
+
#endif /* DEVICE_DRAM_DDR4L_H */
diff --git a/tests/device/Makefile.inc b/tests/device/Makefile.inc
index 10223c52cc..4626c3cf3d 100644
--- a/tests/device/Makefile.inc
+++ b/tests/device/Makefile.inc
@@ -1,7 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
tests-y += i2c-test
+tests-y += ddr4-test
i2c-test-srcs += tests/device/i2c-test.c
i2c-test-srcs += src/device/i2c.c
i2c-test-mocks += platform_i2c_transfer
+
+ddr4-test-srcs += tests/device/ddr4-test.c
+ddr4-test-srcs += tests/stubs/console.c
+ddr4-test-srcs += src/device/dram/ddr4.c \ No newline at end of file
diff --git a/tests/device/ddr4-test.c b/tests/device/ddr4-test.c
new file mode 100644
index 0000000000..0a9831da75
--- /dev/null
+++ b/tests/device/ddr4-test.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/dram/ddr4.h>
+#include <tests/test.h>
+
+static void ddr4_speed_mhz_to_mts_test(void **state)
+{
+ assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(0));
+ assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(667));
+
+ assert_int_equal(1600, ddr4_speed_mhz_to_reported_mts(668));
+ assert_int_equal(1600, ddr4_speed_mhz_to_reported_mts(800));
+
+ assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(801));
+ assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(933));
+ assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(934));
+
+ assert_int_equal(2133, ddr4_speed_mhz_to_reported_mts(1066));
+ assert_int_equal(2133, ddr4_speed_mhz_to_reported_mts(1067));
+
+ assert_int_equal(2400, ddr4_speed_mhz_to_reported_mts(1200));
+
+ assert_int_equal(2666, ddr4_speed_mhz_to_reported_mts(1333));
+
+ assert_int_equal(2933, ddr4_speed_mhz_to_reported_mts(1466));
+
+ assert_int_equal(3200, ddr4_speed_mhz_to_reported_mts(1467));
+ assert_int_equal(3200, ddr4_speed_mhz_to_reported_mts(1600));
+
+ assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(1601));
+ assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(INT16_MAX));
+}
+
+int main(void)
+{
+ const struct CMUnitTest tests[] = {
+ cmocka_unit_test(ddr4_speed_mhz_to_mts_test)
+ };
+
+ return cmocka_run_group_tests(tests, NULL, NULL);
+}