summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/soc/intel/apollolake/acpi/xhci.asl22
-rw-r--r--src/soc/intel/apollolake/acpi/xhci_apl_ports.asl34
-rw-r--r--src/soc/intel/apollolake/acpi/xhci_glk_ports.asl35
-rw-r--r--src/soc/intel/apollolake/chip.c3
4 files changed, 77 insertions, 17 deletions
diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl
index 9f8503341d..9f7304bb57 100644
--- a/src/soc/intel/apollolake/acpi/xhci.asl
+++ b/src/soc/intel/apollolake/acpi/xhci.asl
@@ -34,22 +34,10 @@ Device (XHCI) {
/* Root Hub */
Name (_ADR, Zero)
- /* USB2 */
- Device (HS01) { Name (_ADR, 1) }
- Device (HS02) { Name (_ADR, 2) }
- Device (HS03) { Name (_ADR, 3) }
- Device (HS04) { Name (_ADR, 4) }
- Device (HS05) { Name (_ADR, 5) }
- Device (HS06) { Name (_ADR, 6) }
- Device (HS07) { Name (_ADR, 7) }
- Device (HS08) { Name (_ADR, 8) }
-
- /* USB3 */
- Device (SS01) { Name (_ADR, 9) }
- Device (SS02) { Name (_ADR, 10) }
- Device (SS03) { Name (_ADR, 11) }
- Device (SS04) { Name (_ADR, 12) }
- Device (SS05) { Name (_ADR, 13) }
- Device (SS06) { Name (_ADR, 14) }
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include "xhci_glk_ports.asl"
+#else
+#include "xhci_apl_ports.asl"
+#endif
}
}
diff --git a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl
new file mode 100644
index 0000000000..ebb3e8cd99
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 9) }
+Device (SS02) { Name (_ADR, 10) }
+Device (SS03) { Name (_ADR, 11) }
+Device (SS04) { Name (_ADR, 12) }
+Device (SS05) { Name (_ADR, 13) }
+Device (SS06) { Name (_ADR, 14) }
diff --git a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl
new file mode 100644
index 0000000000..e3b045cc2a
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+Device (HS09) { Name (_ADR, 9) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 10) }
+Device (SS02) { Name (_ADR, 11) }
+Device (SS03) { Name (_ADR, 12) }
+Device (SS04) { Name (_ADR, 13) }
+Device (SS05) { Name (_ADR, 14) }
+Device (SS06) { Name (_ADR, 15) }
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index cddfe4436f..de33e8217b 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -121,6 +121,9 @@ const char *soc_acpi_name(const struct device *dev)
case 5: return "HS06";
case 6: return "HS07";
case 7: return "HS08";
+ case 8:
+ if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+ return "HS09";
}
break;
case 3: