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-rw-r--r--src/acpi/dsdt_top.asl13
-rw-r--r--src/soc/amd/stoneyridge/acpi/pci_int.asl4
-rw-r--r--src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl3
-rw-r--r--src/southbridge/amd/agesa/hudson/acpi/pci_int.asl4
-rw-r--r--src/southbridge/amd/cimx/sb800/acpi/pcie.asl4
-rw-r--r--src/southbridge/amd/pi/hudson/acpi/pci_int.asl4
6 files changed, 14 insertions, 18 deletions
diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index 160a53fc7b..eece7f7f22 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -32,9 +32,14 @@ Method (_PIC, 1)
}
#if CONFIG(MMCONF_SUPPORT)
-/* Base address of PCIe config space */
-Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
+Scope(\_SB) {
+ /* Base address of PCIe config space */
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
-/* Length of PCIe config space, 1MB each bus */
-Name(PCLN, CONFIG_MMCONF_LENGTH)
+ /* Length of PCIe config space, 1MB each bus */
+ Name(PCLN, CONFIG_MMCONF_LENGTH)
+
+ /* PCIe Configuration Space */
+ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
+}
#endif
diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl
index 0f1feef05a..e905c9738c 100644
--- a/src/soc/amd/stoneyridge/acpi/pci_int.asl
+++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl
@@ -1,8 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
- /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
- OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
* The 8 comes from 8 functions per device, and 4096 bytes per function config space
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index 40e882c004..4580b772f0 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -284,8 +284,7 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
PGA3, 8 ,
}
-OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000)
-Field(FCFG, DwordAcc, NoLock, Preserve)
+Field(PCFG, DwordAcc, NoLock, Preserve)
{
/* XHCI */
Offset(0x00080010), /* Base address */
diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
index 37b2333b29..6ff81cd66f 100644
--- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
+++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
@@ -1,8 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
- /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
- OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
* The 8 comes from 8 functions per device, and 4096 bytes per function config space
diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
index 65ac920efa..f69ba1db24 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
@@ -29,9 +29,7 @@ Scope(\) {
}
Scope(\_SB) {
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
* The 8 comes from 8 functions per device, and 4096 bytes per function config space
diff --git a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl
index 37b2333b29..6ff81cd66f 100644
--- a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl
@@ -1,8 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
- /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
- OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
* The 8 comes from 8 functions per device, and 4096 bytes per function config space