diff options
| -rw-r--r-- | src/soc/intel/baytrail/southcluster.c | 34 |
1 files changed, 12 insertions, 22 deletions
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index dcc48e9c17..45c588a165 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -28,9 +28,8 @@ #include "chip.h" #include <acpi/acpigen.h> -static inline void -add_mmio_resource(struct device *dev, int i, unsigned long addr, - unsigned long size) +static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, + unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } @@ -58,8 +57,7 @@ static inline int io_range_in_default(int base, int size) return 0; /* Is it entirely contained? */ - if (base >= LPC_DEFAULT_IO_RANGE_LOWER && - (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) + if (base >= LPC_DEFAULT_IO_RANGE_LOWER && (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) return 1; /* This will return not in range for partial overlaps */ @@ -70,8 +68,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(struct device *dev, int base, int size, - int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -113,11 +110,6 @@ static void sc_read_resources(struct device *dev) sc_add_io_resources(dev); } -static void sc_rtc_init(void) -{ - cmos_init(rtc_failure()); -} - /* * The UART hardware loses power while in suspend. Because of this the kernel * can hang because it doesn't re-initialize serial ports it is using for @@ -176,15 +168,14 @@ static void sc_init(struct device *dev) /* Route SCI to IRQ9 */ write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); - sc_rtc_init(); + cmos_init(rtc_failure()); if (config->disable_slp_x_stretch_sus_fail) { printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); - write32(gen_pmcon1, - read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); + write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); + } else { - write32(gen_pmcon1, - read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); + write32(gen_pmcon1, read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } if (acpi_is_wakeup_s3()) @@ -200,7 +191,7 @@ static void sc_disable_devfn(struct device *dev) { void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); - uint32_t mask = 0; + uint32_t mask = 0; uint32_t mask2 = 0; switch (dev->path.pci.devfn) { @@ -475,8 +466,7 @@ void southcluster_enable_dev(struct device *dev) /* Ensure memory, io, and bus master are all disabled */ reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config16(dev, PCI_COMMAND, reg16); /* Place device in D3Hot */ @@ -522,7 +512,7 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .acpi_inject_dsdt = southcluster_inject_dsdt, - .write_acpi_tables = acpi_write_hpet, + .write_acpi_tables = acpi_write_hpet, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_static_bus, @@ -546,7 +536,7 @@ static void finalize_chipset(void *unused) void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); void *etr = (void *)(PMC_BASE_ADDRESS + ETR); - u8 *spi = (u8 *)SPI_BASE_ADDRESS; + uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct spi_config cfg; /* Set the lock enable on the BIOS control register */ |