diff options
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/graphics.c | 38 | ||||
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/acpi.c | 39 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/gfx.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/opregion.c | 67 | ||||
| -rw-r--r-- | src/soc/intel/common/opregion.h | 24 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/ramstage.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/graphics.c | 32 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 1 |
13 files changed, 15 insertions, 203 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index affa7edc7f..fcb1ef757f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -94,7 +94,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE - select SOC_INTEL_COMMON_GFX_OPREGION select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER @@ -106,6 +105,8 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP select HAVE_FSP_GOP select NO_UART_ON_SUPERIO + select INTEL_GMA_ACPI + select INTEL_GMA_SWSMISCI config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 55b98617f8..485778833f 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -21,7 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <intelblocks/graphics.h> -#include <soc/intel/common/opregion.h> +#include <drivers/intel/gma/opregion.h> uintptr_t fsp_soc_get_igd_bar(void) { @@ -32,45 +32,15 @@ uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; - uint16_t reg16; printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); opregion = (igd_opregion_t *)current; - if (init_igd_opregion(opregion) != CB_SUCCESS) + if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) return current; - current += sizeof(igd_opregion_t); - - opregion->mailbox1.clid = 1; - - /* TODO Initialize Mailbox 3 */ - opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; - opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; - opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ - opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; - opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; - opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; - opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; - opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; - opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; - opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; - opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; - opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; - opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; - opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; - opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; - - /* - * TODO This needs to happen in S3 resume, too. - * Maybe it should move to the finalize handler. - */ - - pci_write_config32(device, ASLS, (uintptr_t)opregion); - reg16 = pci_read_config16(device, SWSCI); - reg16 &= ~(1 << 0); - reg16 |= (1 << 15); - pci_write_config16(device, SWSCI, reg16); + /* FIXME: Add platform specific mailbox initialization */ + current += sizeof(igd_opregion_t); return acpi_align_current(current); } diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index dc2f40de1d..1154c041d1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -48,7 +48,8 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP select GENERIC_GPIO_LIB - select SOC_INTEL_COMMON_GFX_OPREGION + select INTEL_GMA_ACPI + select INTEL_GMA_SWSMISCI config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 61ae20354c..61ad03d388 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -31,7 +31,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <ec/google/chromeec/ec.h> -#include <soc/intel/common/opregion.h> +#include <drivers/intel/gma/opregion.h> #include <rules.h> #include <soc/acpi.h> #include <soc/gfx.h> @@ -476,40 +476,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) /* Initialize IGD OpRegion, called from ACPI code */ static int update_igd_opregion(igd_opregion_t *opregion) { - u16 reg16; - struct device *igd; - - /* TODO Initialize Mailbox 1 */ - opregion->mailbox1.clid = 1; - - /* TODO Initialize Mailbox 3 */ - opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; - opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; - opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ - opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; - opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; - opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; - opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; - opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; - opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; - opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; - opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; - opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; - opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; - opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; - opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; - - /* - * TODO This needs to happen in S3 resume, too. - * Maybe it should move to the finalize handler - */ - igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); - - pci_write_config32(igd, ASLS, (u32)opregion); - reg16 = pci_read_config16(igd, SWSCI); - reg16 &= ~(1 << 0); - reg16 |= (1 << 15); - pci_write_config16(igd, SWSCI, reg16); + /* FIXME: Add platform specific mailbox initialization */ return 0; } @@ -528,7 +495,7 @@ unsigned long southcluster_write_acpi_tables(device_t device, printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); opregion = (igd_opregion_t *)current; - init_igd_opregion(opregion); + intel_gma_init_igd_opregion(opregion); update_igd_opregion(opregion); current += sizeof(igd_opregion_t); current = acpi_align_current(current); diff --git a/src/soc/intel/braswell/include/soc/gfx.h b/src/soc/intel/braswell/include/soc/gfx.h index 5a51620333..c6b802fc42 100644 --- a/src/soc/intel/braswell/include/soc/gfx.h +++ b/src/soc/intel/braswell/include/soc/gfx.h @@ -63,9 +63,6 @@ #define APERTURE_SIZE_256MB (1 << 1) #define APERTURE_SIZE_512MB (3 << 1) -#define SWSCI 0xe8 /* SWSCI enable */ -#define ASLS 0xfc /* OpRegion Base */ - /* Panel control registers */ #define HOTPLUG_CTRL 0x61110 #define PP_CONTROL 0x61204 diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 95c09c78c4..c4e6514b85 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -50,10 +50,6 @@ config MMA_BLOBS_PATH default "3rdparty/blobs/soc/intel/kabylake/mma-blobs" if SOC_INTEL_KABYLAKE default "3rdparty/blobs/soc/intel/skylake/mma-blobs" if SOC_INTEL_SKYLAKE -config SOC_INTEL_COMMON_GFX_OPREGION - bool - default n - config SOC_INTEL_COMMON_SMI bool default n diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index e56ac7daaf..bfd6a77703 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -23,7 +23,6 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c bootblock-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c diff --git a/src/soc/intel/common/opregion.c b/src/soc/intel/common/opregion.c deleted file mode 100644 index f35e12a0e7..0000000000 --- a/src/soc/intel/common/opregion.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <cbmem.h> - -#include <drivers/intel/gma/opregion.h> -#include "opregion.h" -#include "vbt.h" - -enum cb_err init_igd_opregion(igd_opregion_t *opregion) -{ - optionrom_vbt_t *vbt; - optionrom_vbt_t *ext_vbt; - - vbt = locate_vbt(); - - if (!vbt) { - printk(BIOS_ERR, "VBT couldn't be read\n"); - return CB_ERR; - } - - memset(opregion, 0, sizeof(igd_opregion_t)); - - memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(opregion->header.signature)); - memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, - ARRAY_SIZE(vbt->coreblock_biosbuild)); - /* Extended VBT support */ - if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) { - ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size); - - if (ext_vbt == NULL) { - printk(BIOS_ERR, "Unable to add Ext VBT to cbmem!\n"); - return CB_ERR; - } - - memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); - opregion->mailbox3.rvda = (uintptr_t)ext_vbt; - opregion->mailbox3.rvds = vbt->hdr_vbt_size; - } else { - /* Raw VBT size which can fit in gvd1 */ - memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size); - } - - /* 8KiB */ - opregion->header.size = sizeof(igd_opregion_t) / KiB; - opregion->header.version = IGD_OPREGION_VERSION << 24; - - /* FIXME We just assume we're mobile for now */ - opregion->header.mailboxes = MAILBOXES_MOBILE; - - return CB_SUCCESS; -} diff --git a/src/soc/intel/common/opregion.h b/src/soc/intel/common/opregion.h deleted file mode 100644 index 7945a49ace..0000000000 --- a/src/soc/intel/common/opregion.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _COMMON_OPREGION_H_ -#define _COMMON_OPREGION_H_ - -#include <drivers/intel/gma/opregion.h> - -/* Loads vbt and initializes opregion. Returns non-zero on success */ -enum cb_err init_igd_opregion(igd_opregion_t *opregion); - -#endif /* _COMMON_OPREGION_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/ramstage.h b/src/soc/intel/denverton_ns/include/soc/ramstage.h index 63ed4327f2..c53d811462 100644 --- a/src/soc/intel/denverton_ns/include/soc/ramstage.h +++ b/src/soc/intel/denverton_ns/include/soc/ramstage.h @@ -19,7 +19,6 @@ #include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> -#include <soc/intel/common/opregion.h> void denverton_init_cpus(device_t dev); void mainboard_silicon_init_params(FSPS_UPD *params); diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 2322a5f2c7..cf947a7670 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_INTEL_FIRMWARE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER + select INTEL_GMA_ACPI select IOAPIC select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE @@ -87,7 +88,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI - select SOC_INTEL_COMMON_GFX_OPREGION select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SSE2 diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index f39f39c6a0..95a37d673d 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -18,7 +18,7 @@ #include <device/pci.h> #include <drivers/intel/gma/i915_reg.h> #include <intelblocks/graphics.h> -#include <soc/intel/common/opregion.h> +#include <drivers/intel/gma/opregion.h> #include <soc/ramstage.h> uintptr_t fsp_soc_get_igd_bar(void) @@ -65,33 +65,7 @@ void graphics_soc_init(struct device *dev) /* Initialize IGD OpRegion, called from ACPI code */ static void update_igd_opregion(igd_opregion_t *opregion) { - u16 reg16; - - opregion->mailbox1.clid = 1; - - /* Initialize Mailbox 3 */ - opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; - opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; - opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ - opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; - opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; - opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; - opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; - opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; - opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; - opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; - opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; - opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; - opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; - opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; - opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; - - /* TODO This may need to happen in S3 resume */ - pci_write_config32(SA_DEV_IGD, ASLS, (u32)opregion); - reg16 = pci_read_config16(SA_DEV_IGD, SWSCI); - reg16 &= ~GSSCIE; - reg16 |= SMISCISEL; - pci_write_config16(SA_DEV_IGD, SWSCI, reg16); + /* FIXME: Add platform specific mailbox initialization */ } uintptr_t graphics_soc_write_acpi_opregion(struct device *device, @@ -110,7 +84,7 @@ uintptr_t graphics_soc_write_acpi_opregion(struct device *device, printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); opregion = (igd_opregion_t *)current; - if (init_igd_opregion(opregion) != CB_SUCCESS) + if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) return current; update_igd_opregion(opregion); diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index 23443c33d3..e75b350049 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -21,7 +21,6 @@ #include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> -#include <soc/intel/common/opregion.h> #define FSP_SIL_UPD FSP_S_CONFIG #define FSP_MEM_UPD FSP_M_CONFIG |