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-rw-r--r--src/northbridge/intel/sandybridge/raminit.c31
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c3
2 files changed, 31 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 2728037ac9..06b4d1ec45 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -416,10 +416,41 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
set_scrambling_seed(&ctrl);
+ if (!s3resume && ctrl.ecc_enabled)
+ channel_scrub(&ctrl);
+
set_normal_operation(&ctrl);
final_registers(&ctrl);
+ /* can't do this earlier because it needs to be done in normal operation */
+ if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) {
+ uint32_t i, tseg = pci_read_config32(HOST_BRIDGE, TSEGMB);
+
+ printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n",
+ tseg);
+
+ /*
+ * This test helps to debug the ECC scrubbing.
+ * It likely tests every channel/rank, as rank interleave and enhanced
+ * interleave are enabled, but there's no guarantee for it.
+ */
+
+ /* Skip first MB to avoid special case for A-seg and test up to TSEG */
+ for (i = 1; i < tseg >> 20; i++) {
+ for (int j = 0; j < 1 * MiB; j += 4096) {
+ uintptr_t addr = i * MiB + j;
+ if (read32((u32 *)addr) == 0)
+ continue;
+
+ printk(BIOS_ERR, "RAMINIT: ECC scrub: DRAM not cleared at"
+ " addr 0x%lx\n", addr);
+ break;
+ }
+ }
+ printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n");
+ }
+
/* Zone config */
dram_zones(&ctrl, 0);
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 62715a1c23..c23a5acff0 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -687,9 +687,6 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_
err = channel_test(ctrl);
if (err)
return err;
-
- if (ctrl->ecc_enabled)
- channel_scrub(ctrl);
}
/* Set MAD-DIMM registers */