summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/arch/riscv/Makefile.inc5
-rw-r--r--src/arch/riscv/include/stdint.h3
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index dab661eb8d..85bec43c50 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -3,6 +3,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2014 The ChromiumOS Authors
+## Copyright (C) 2018 HardenedLinux
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -82,8 +83,6 @@ romstage-y += \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
-romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-
# Build the romstage
$(objcbfs)/romstage.debug: $$(romstage-objs)
@@ -116,8 +115,6 @@ ramstage-y += \
$(eval $(call create_class_compiler,rmodules,riscv))
-ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
# Build the ramstage
diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h
index 446a1367e9..19808662eb 100644
--- a/src/arch/riscv/include/stdint.h
+++ b/src/arch/riscv/include/stdint.h
@@ -73,4 +73,7 @@ typedef uint8_t bool;
typedef s64 intptr_t;
typedef u64 uintptr_t;
+/* FIXME: This is used in some print code and may be removed in the future. */
+#define PRIu64 "llu"
+
#endif /* RISCV_STDINT_H */