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-rw-r--r--Documentation/mainboard/system76/lemp9.md73
-rw-r--r--configs/config.system76_lemp95
-rw-r--r--src/mainboard/system76/Kconfig16
-rw-r--r--src/mainboard/system76/Kconfig.name2
-rw-r--r--src/mainboard/system76/lemp9/Kconfig103
-rw-r--r--src/mainboard/system76/lemp9/Kconfig.name2
-rw-r--r--src/mainboard/system76/lemp9/Makefile.inc4
-rw-r--r--src/mainboard/system76/lemp9/acpi/ac.asl35
-rw-r--r--src/mainboard/system76/lemp9/acpi/battery.asl183
-rw-r--r--src/mainboard/system76/lemp9/acpi/buttons.asl26
-rw-r--r--src/mainboard/system76/lemp9/acpi/ec.asl231
-rw-r--r--src/mainboard/system76/lemp9/acpi/ec_ram.asl188
-rw-r--r--src/mainboard/system76/lemp9/acpi/gpe.asl24
-rw-r--r--src/mainboard/system76/lemp9/acpi/hid.asl63
-rw-r--r--src/mainboard/system76/lemp9/acpi/lid.asl36
-rw-r--r--src/mainboard/system76/lemp9/acpi/mainboard.asl28
-rw-r--r--src/mainboard/system76/lemp9/acpi/s76.asl97
-rw-r--r--src/mainboard/system76/lemp9/acpi/sleep.asl24
-rw-r--r--src/mainboard/system76/lemp9/board_info.txt8
-rw-r--r--src/mainboard/system76/lemp9/bootblock.c23
-rw-r--r--src/mainboard/system76/lemp9/data.vbtbin0 -> 4608 bytes
-rw-r--r--src/mainboard/system76/lemp9/devicetree.cb238
-rw-r--r--src/mainboard/system76/lemp9/dsdt.asl47
-rw-r--r--src/mainboard/system76/lemp9/gpio.h547
-rw-r--r--src/mainboard/system76/lemp9/hda_verb.c48
-rw-r--r--src/mainboard/system76/lemp9/ramstage.c24
-rw-r--r--src/mainboard/system76/lemp9/romstage.c97
-rw-r--r--src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex33
28 files changed, 2205 insertions, 0 deletions
diff --git a/Documentation/mainboard/system76/lemp9.md b/Documentation/mainboard/system76/lemp9.md
new file mode 100644
index 0000000000..9739484820
--- /dev/null
+++ b/Documentation/mainboard/system76/lemp9.md
@@ -0,0 +1,73 @@
+# System76 Lemur Pro (lemp9)
+
+## Specs
+
+- CPU
+ - Intel i7-10510U
+ - Intel i5-10210U
+- EC
+ - ITE IT5570E running https://github.com/system76/ec
+ - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
+ - Battery
+ - Charger, using AC adapter or USB-C PD
+ - Suspend/resume
+ - Touchpad
+- GPU
+ - Intel UHD Graphics 620
+ - GOP driver is recommended, VBT is provided
+ - eDP 14-inch 1920x1080 LCD
+ - HDMI video
+ - USB-C DisplayPort video
+- Memory
+ - Channel 0: 8-GB on-board DDR4 Samsung K4AAG165WA-BCTD
+ - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM
+- Networking
+ - M.2 PCIe/CNVi WiFi/Bluetooth
+- Sound
+ - Realtek ALC293D
+ - Internal speaker
+ - Internal microphone
+ - Combined headphone/microphone 3.5-mm jack
+ - HDMI audio
+ - USB-C DisplayPort audio
+- Storage
+ - M.2 PCIe/SATA SSD-1
+ - M.2 PCIe/SATA SSD-2
+ - RTS5227S MicroSD card reader
+- USB
+ - 1280x720 CCD camera
+ - USB 3.1 Gen 2 Type-C (left)
+ - USB 3.1 Gen 2 Type-A (left)
+ - USB 3.1 Gen 1 Type-A (right)
+
+## Building coreboot
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.system76_lemp9
+make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | no |
++---------------------+------------+
+| Vendor | GigaDevice |
++---------------------+------------+
+| Model | GD25Q128C |
++---------------------+------------+
+| Size | 16 MiB |
++---------------------+------------+
+| Package | SOIC-8 |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+| External flashing | yes |
++---------------------+------------+
+```
diff --git a/configs/config.system76_lemp9 b/configs/config.system76_lemp9
new file mode 100644
index 0000000000..d9d98facd7
--- /dev/null
+++ b/configs/config.system76_lemp9
@@ -0,0 +1,5 @@
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_BOARD_SYSTEM76_LEMP9=y
+CONFIG_PAYLOAD_TIANOCORE=y
+CONFIG_RUN_FSP_GOP=y
+CONFIG_SMMSTORE=y
diff --git a/src/mainboard/system76/Kconfig b/src/mainboard/system76/Kconfig
new file mode 100644
index 0000000000..62034a4222
--- /dev/null
+++ b/src/mainboard/system76/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_SYSTEM76
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/system76/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/system76/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "System76"
+
+endif
diff --git a/src/mainboard/system76/Kconfig.name b/src/mainboard/system76/Kconfig.name
new file mode 100644
index 0000000000..7155721bee
--- /dev/null
+++ b/src/mainboard/system76/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_SYSTEM76
+ bool "System76"
diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig
new file mode 100644
index 0000000000..a612503b6a
--- /dev/null
+++ b/src/mainboard/system76/lemp9/Kconfig
@@ -0,0 +1,103 @@
+if BOARD_SYSTEM76_LEMP9
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ADD_FSP_BINARIES
+ select BOARD_ROMSIZE_KB_16384
+ select EC_ACPI
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_SMI_HANDLER
+ select GENERIC_SPD_BIN
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_LPSS_UART_FOR_CONSOLE
+# Chip select 2 is not yet supported by intel fast_spi
+# select MAINBOARD_HAS_SPI_TPM_CR50
+# select MAINBOARD_HAS_TPM2
+ select NO_UART_ON_SUPERIO
+ select SOC_INTEL_COMETLAKE
+ select SOC_INTEL_COMMON_BLOCK_HDA
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SPD_READ_BY_WORD
+ select SYSTEM_TYPE_LAPTOP
+ select USE_BLOBS
+ select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+ string
+ default system76/lemp9
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "lemp9"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+ string
+ default "Lemur Pro"
+
+config MAINBOARD_VERSION
+ string
+ default "lemp9"
+
+config CBFS_SIZE
+ hex
+ default 0xA00000
+
+config SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1558
+
+config SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x1401
+
+config CONSOLE_POST
+ bool
+ default y
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config MAX_CPUS
+ int
+ default 8
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,9b41.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,9b41"
+
+config FSP_M_XIP
+ bool
+ default y
+
+config POST_DEVICE
+ bool
+ default n
+
+# Chip select 2 is not yet supported by intel fast_spi
+#config DRIVER_TPM_SPI_BUS
+# hex
+# default 0x0
+#
+#config DRIVER_TPM_SPI_CHIP
+# int
+# default 2
+
+endif
diff --git a/src/mainboard/system76/lemp9/Kconfig.name b/src/mainboard/system76/lemp9/Kconfig.name
new file mode 100644
index 0000000000..4a4ab68597
--- /dev/null
+++ b/src/mainboard/system76/lemp9/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_LEMP9
+ bool "lemp9"
diff --git a/src/mainboard/system76/lemp9/Makefile.inc b/src/mainboard/system76/lemp9/Makefile.inc
new file mode 100644
index 0000000000..3d742d6e13
--- /dev/null
+++ b/src/mainboard/system76/lemp9/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+SPD_SOURCES = samsung-K4AAG165WA-BCTD
diff --git a/src/mainboard/system76/lemp9/acpi/ac.asl b/src/mainboard/system76/lemp9/acpi/ac.asl
new file mode 100644
index 0000000000..6574c61e41
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/ac.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID
+ Name (_PCL, Package (0x01) // _PCL: Power Consumer List
+ {
+ _SB
+ })
+
+ Name (ACFG, One)
+
+ Method (_PSR, 0, NotSerialized) // _PSR: Power Source
+ {
+ Return (ACFG)
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/mainboard/system76/lemp9/acpi/battery.asl b/src/mainboard/system76/lemp9/acpi/battery.asl
new file mode 100644
index 0000000000..c1e6c6ce1d
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/battery.asl
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (BAT0)
+{
+ Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PCL, Package (0x01) // _PCL: Power Consumer List
+ {
+ _SB
+ })
+ Name (BFCC, Zero)
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (^^PCI0.LPCB.EC0.ECOK)
+ {
+ If (^^PCI0.LPCB.EC0.BAT0)
+ {
+ Return (0x1F)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+
+ Name (PBIF, Package (0x0D)
+ {
+ One,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ One,
+ 0x39D0,
+ Zero,
+ Zero,
+ 0x40,
+ 0x40,
+ "BAT",
+ "0001",
+ "LION",
+ "Notebook"
+ })
+ Method (IVBI, 0, NotSerialized)
+ {
+ PBIF [One] = 0xFFFFFFFF
+ PBIF [0x02] = 0xFFFFFFFF
+ PBIF [0x04] = 0xFFFFFFFF
+ PBIF [0x09] = " "
+ PBIF [0x0A] = " "
+ PBIF [0x0B] = " "
+ PBIF [0x0C] = " "
+ BFCC = Zero
+ }
+
+ Method (UPBI, 0, NotSerialized)
+ {
+ If (^^PCI0.LPCB.EC0.BAT0)
+ {
+ Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
+ PBIF [One] = Local0
+ Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
+ PBIF [0x02] = Local0
+ BFCC = Local0
+ Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
+ PBIF [0x04] = Local0
+ Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
+ PBIF [0x05] = Local0
+ Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
+ PBIF [0x06] = Local0
+ PBIF [0x09] = "BAT"
+ PBIF [0x0A] = "0001"
+ PBIF [0x0B] = "LION"
+ PBIF [0x0C] = "Notebook"
+ }
+ Else
+ {
+ IVBI ()
+ }
+ }
+
+ Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
+ {
+ If (^^PCI0.LPCB.EC0.ECOK)
+ {
+ UPBI ()
+ }
+ Else
+ {
+ IVBI ()
+ }
+
+ Return (PBIF) /* \_SB_.BAT0.PBIF */
+ }
+
+ Name (PBST, Package (0x04)
+ {
+ Zero,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0x3D90
+ })
+ Method (IVBS, 0, NotSerialized)
+ {
+ PBST [Zero] = Zero
+ PBST [One] = 0xFFFFFFFF
+ PBST [0x02] = 0xFFFFFFFF
+ PBST [0x03] = 0x2710
+ }
+
+ Method (UPBS, 0, NotSerialized)
+ {
+ If (^^PCI0.LPCB.EC0.BAT0)
+ {
+ Local0 = Zero
+ Local1 = Zero
+ If (^^AC.ACFG)
+ {
+ If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
+ {
+ Local0 |= 0x02
+ Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
+ }
+ }
+ Else
+ {
+ Local0 |= One
+ Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
+ }
+
+ Local7 = (Local1 & 0x8000)
+ If ((Local7 == 0x8000))
+ {
+ Local1 ^= 0xFFFF
+ }
+
+ Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
+ Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
+ PBST [Zero] = Local0
+ PBST [One] = Local1
+ PBST [0x02] = Local2
+ PBST [0x03] = Local3
+ If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+ }
+ Else
+ {
+ IVBS ()
+ }
+ }
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ If (^^PCI0.LPCB.EC0.ECOK)
+ {
+ UPBS ()
+ }
+ Else
+ {
+ IVBS ()
+ }
+
+ Return (PBST) /* \_SB_.BAT0.PBST */
+ }
+}
diff --git a/src/mainboard/system76/lemp9/acpi/buttons.asl b/src/mainboard/system76/lemp9/acpi/buttons.asl
new file mode 100644
index 0000000000..62847b5c09
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/buttons.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (PWRB)
+{
+ Name (_HID, EisaId ("PNP0C0C"))
+ Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 })
+}
+
+Device (SLPB)
+{
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 })
+}
diff --git a/src/mainboard/system76/lemp9/acpi/ec.asl b/src/mainboard/system76/lemp9/acpi/ec.asl
new file mode 100644
index 0000000000..c26670a009
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/ec.asl
@@ -0,0 +1,231 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (EC0)
+{
+ Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
+ Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0062, // Range Minimum
+ 0x0062, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0066, // Range Minimum
+ 0x0066, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ })
+
+ #include "acpi/ec_ram.asl"
+
+ Name (ECOK, Zero)
+ Method (_REG, 2, Serialized) // _REG: Region Availability
+ {
+ Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1))))
+ If (((Arg0 == 0x03) && (Arg1 == One))) {
+ // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
+ ECOS = 1
+
+ // Enable software display brightness keys
+ WINF = 1
+
+ // Set current AC state
+ ^^^^AC.ACFG = ADP
+ // Update battery information and status
+ ^^^^BAT0.UPBI()
+ ^^^^BAT0.UPBS()
+
+ PNOT ()
+
+ // EC is now available
+ ECOK = Arg1
+
+ // Reset System76 Device
+ ^^^^S76D.RSET()
+ }
+ }
+
+ Method (PTS, 1, Serialized) {
+ Debug = Concatenate("EC: PTS: ", ToHexString(Arg0))
+ If (ECOK) {
+ // Clear wake cause
+ WFNO = Zero
+ }
+ }
+
+ Method (WAK, 1, Serialized) {
+ Debug = Concatenate("EC: WAK: ", ToHexString(Arg0))
+ If (ECOK) {
+ // Set current AC state
+ ^^^^AC.ACFG = ADP
+
+ // Update battery information and status
+ ^^^^BAT0.UPBI()
+ ^^^^BAT0.UPBS()
+
+ // Notify of changes
+ Notify(^^^^AC, Zero)
+ Notify(^^^^BAT0, Zero)
+
+ Sleep (1000)
+
+ // Reset System76 Device
+ ^^^^S76D.RSET()
+ }
+ }
+
+ Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
+ {
+ Debug = "EC: Touchpad Toggle"
+ }
+
+ Method (_Q0B, 0, NotSerialized) // Screen Toggle
+ {
+ Debug = "EC: Screen Toggle"
+ }
+
+ Method (_Q0C, 0, NotSerialized) // Mute
+ {
+ Debug = "EC: Mute"
+ }
+
+ Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
+ {
+ Debug = "EC: Keyboard Backlight"
+ }
+
+ Method (_Q0E, 0, NotSerialized) // Volume Down
+ {
+ Debug = "EC: Volume Down"
+ }
+
+ Method (_Q0F, 0, NotSerialized) // Volume Up
+ {
+ Debug = "EC: Volume Up"
+ }
+
+ Method (_Q10, 0, NotSerialized) // Switch Video Mode
+ {
+ Debug = "EC: Switch Video Mode"
+ }
+
+ Method (_Q11, 0, NotSerialized) // Brightness Down
+ {
+ Debug = "EC: Brightness Down"
+ ^^^^HIDD.HPEM (20)
+ }
+
+ Method (_Q12, 0, NotSerialized) // Brightness Up
+ {
+ Debug = "EC: Brightness Up"
+ ^^^^HIDD.HPEM (19)
+ }
+
+ Method (_Q13, 0, NotSerialized) // Camera Toggle
+ {
+ Debug = "EC: Camera Toggle"
+ }
+
+ Method (_Q14, 0, NotSerialized) // Airplane Mode
+ {
+ Debug = "EC: Airplane Mode"
+ // Only send HIDD message when hardware airplane mode not in use
+ If (ECOS == 2) {
+ ^^^^HIDD.HPEM (8)
+ }
+ }
+
+ Method (_Q15, 0, NotSerialized) // Suspend Button
+ {
+ Debug = "EC: Suspend Button"
+ Notify (SLPB, 0x80)
+ }
+
+ Method (_Q16, 0, NotSerialized) // AC Detect
+ {
+ Debug = "EC: AC Detect"
+ ^^^^AC.ACFG = ADP
+ Notify (AC, 0x80) // Status Change
+ Sleep (0x01F4)
+ If (BAT0)
+ {
+ Notify (^^^^BAT0, 0x81) // Information Change
+ Sleep (0x32)
+ Notify (^^^^BAT0, 0x80) // Status Change
+ Sleep (0x32)
+ }
+ }
+
+ Method (_Q17, 0, NotSerialized) // BAT0 Update
+ {
+ Debug = "EC: BAT0 Update (17)"
+ Notify (^^^^BAT0, 0x81) // Information Change
+ }
+
+ Method (_Q19, 0, NotSerialized) // BAT0 Update
+ {
+ Debug = "EC: BAT0 Update (19)"
+ Notify (^^^^BAT0, 0x81) // Information Change
+ }
+
+ Method (_Q1B, 0, NotSerialized) // Lid Close
+ {
+ Debug = "EC: Lid Close"
+ Notify (LID0, 0x80)
+ }
+
+ Method (_Q1C, 0, NotSerialized) // Thermal Trip
+ {
+ Debug = "EC: Thermal Trip"
+ /* TODO
+ Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
+ Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
+ */
+ }
+
+ Method (_Q1D, 0, NotSerialized) // Power Button
+ {
+ Debug = "EC: Power Button"
+ Notify (PWRB, 0x80)
+ }
+
+ Method (_Q50, 0, NotSerialized) // Other Events
+ {
+ Local0 = OEM4
+ If (Local0 == 0x8A) {
+ Debug = "EC: White Keyboard Backlight"
+ Notify (^^^^S76D, 0x80)
+ } ElseIf (Local0 == 0x9F) {
+ Debug = "EC: Color Keyboard Toggle"
+ Notify (^^^^S76D, 0x81)
+ } ElseIf (Local0 == 0x81) {
+ Debug = "EC: Color Keyboard Down"
+ Notify (^^^^S76D, 0x82)
+ } ElseIf (Local0 == 0x82) {
+ Debug = "EC: Color Keyboard Up"
+ Notify (^^^^S76D, 0x83)
+ } ElseIf (Local0 == 0x80) {
+ Debug = "EC: Color Keyboard Color Change"
+ Notify (^^^^S76D, 0x84)
+ } Else {
+ Debug = Concatenate("EC: Other: ", ToHexString(Local0))
+ }
+ }
+}
diff --git a/src/mainboard/system76/lemp9/acpi/ec_ram.asl b/src/mainboard/system76/lemp9/acpi/ec_ram.asl
new file mode 100644
index 0000000000..4bb452b6e3
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/ec_ram.asl
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
+Field (ERAM, ByteAcc, Lock, Preserve)
+{
+ NMSG, 8,
+ SLED, 4,
+ Offset (0x02),
+ MODE, 1,
+ FAN0, 1,
+ TME0, 1,
+ TME1, 1,
+ FAN1, 1,
+ , 2,
+ Offset (0x03),
+ LSTE, 1,
+ LSW0, 1,
+ LWKE, 1,
+ WAKF, 1,
+ , 2,
+ PWKE, 1,
+ MWKE, 1,
+ AC0, 8,
+ PSV, 8,
+ CRT, 8,
+ TMP, 8,
+ AC1, 8,
+ BBST, 8,
+ Offset (0x0B),
+ Offset (0x0C),
+ Offset (0x0D),
+ Offset (0x0E),
+ SLPT, 8,
+ SWEJ, 1,
+ SWCH, 1,
+ Offset (0x10),
+ ADP, 1,
+ AFLT, 1,
+ BAT0, 1,
+ BAT1, 1,
+ , 3,
+ PWOF, 1,
+ WFNO, 8,
+ BPU0, 32,
+ BDC0, 32,
+ BFC0, 32,
+ BTC0, 32,
+ BDV0, 32,
+ BST0, 32,
+ BPR0, 32,
+ BRC0, 32,
+ BPV0, 32,
+ BTP0, 16,
+ BRS0, 16,
+ BCW0, 32,
+ BCL0, 32,
+ BCG0, 32,
+ BG20, 32,
+ BMO0, 64,
+ BIF0, 64,
+ BSN0, 32,
+ BTY0, 64,
+ Offset (0x67),
+ Offset (0x68),
+ ECOS, 8,
+ LNXD, 8,
+ ECPS, 8,
+ Offset (0x6C),
+ BTMP, 16,
+ EVTN, 8,
+ Offset (0x72),
+ PRCL, 8,
+ PRC0, 8,
+ PRC1, 8,
+ PRCM, 8,
+ PRIN, 8,
+ PSTE, 8,
+ PCAD, 8,
+ PEWL, 8,
+ PWRL, 8,
+ PECD, 8,
+ PEHI, 8,
+ PECI, 8,
+ PEPL, 8,
+ PEPM, 8,
+ PWFC, 8,
+ PECC, 8,
+ PDT0, 8,
+ PDT1, 8,
+ PDT2, 8,
+ PDT3, 8,
+ PRFC, 8,
+ PRS0, 8,
+ PRS1, 8,
+ PRS2, 8,
+ PRS3, 8,
+ PRS4, 8,
+ PRCS, 8,
+ PEC0, 8,
+ PEC1, 8,
+ PEC2, 8,
+ PEC3, 8,
+ CMDR, 8,
+ CVRT, 8,
+ GTVR, 8,
+ FANT, 8,
+ SKNT, 8,
+ AMBT, 8,
+ MCRT, 8,
+ DIM0, 8,
+ DIM1, 8,
+ PMAX, 8,
+ PPDT, 8,
+ PECH, 8,
+ PMDT, 8,
+ TSD0, 8,
+ TSD1, 8,
+ TSD2, 8,
+ TSD3, 8,
+ CPUP, 16,
+ MCHP, 16,
+ SYSP, 16,
+ CPAP, 16,
+ MCAP, 16,
+ SYAP, 16,
+ CFSP, 16,
+ CPUE, 16,
+ Offset (0xC6),
+ Offset (0xC7),
+ VGAT, 8,
+ OEM1, 8,
+ OEM2, 8,
+ OEM3, 16,
+ OEM4, 8,
+ Offset (0xCE),
+ DUT1, 8,
+ DUT2, 8,
+ RPM1, 16,
+ RPM2, 16,
+ RPM4, 16,
+ Offset (0xD7),
+ DTHL, 8,
+ DTBP, 8,
+ AIRP, 8,
+ WINF, 8,
+ RINF, 8,
+ Offset (0xDD),
+ INF2, 8,
+ MUTE, 1,
+ Offset (0xE0),
+ RPM3, 16,
+ ECKS, 8,
+ Offset (0xE4),
+ , 4,
+ XTUF, 1,
+ EP12, 1,
+ Offset (0xE5),
+ INF3, 8,
+ Offset (0xE7),
+ GFOF, 8,
+ Offset (0xE9),
+ KPCR, 1,
+ Offset (0xEA),
+ Offset (0xF0),
+ PL1T, 16,
+ PL2T, 16,
+ TAUT, 8,
+ Offset (0xF8),
+ FCMD, 8,
+ FDAT, 8,
+ FBUF, 8,
+ FBF1, 8,
+ FBF2, 8,
+ FBF3, 8
+}
diff --git a/src/mainboard/system76/lemp9/acpi/gpe.asl b/src/mainboard/system76/lemp9/acpi/gpe.asl
new file mode 100644
index 0000000000..e68c9cd306
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/gpe.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// GPP_D9 SCI
+Method (_L29, 0, Serialized) {
+ Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+ If (\_SB.PCI0.LPCB.EC0.ECOK) {
+ If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+ Notify(\_SB.LID0, 0x80)
+ }
+ }
+}
diff --git a/src/mainboard/system76/lemp9/acpi/hid.asl b/src/mainboard/system76/lemp9/acpi/hid.asl
new file mode 100644
index 0000000000..1f151d5582
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/hid.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (HIDD)
+{
+ Name (_HID, "INT33D5")
+ Name (HBSY, Zero)
+ Name (HIDX, Zero)
+ Name (HRDY, Zero)
+
+ Method (HDEM, 0, Serialized)
+ {
+ HBSY = Zero
+ Return (HIDX)
+ }
+
+ Method (HDMM, 0, Serialized)
+ {
+ Return (Zero)
+ }
+
+ Method (HDSM, 1, Serialized)
+ {
+ HRDY = Arg0
+ }
+
+ Method (HPEM, 1, Serialized)
+ {
+ HBSY = One
+ HIDX = Arg0
+
+ Notify (HIDD, 0xC0)
+ Local0 = Zero
+ While (((Local0 < 0xFA) && HBSY))
+ {
+ Sleep (0x04)
+ Local0++
+ }
+
+ If ((HBSY == One))
+ {
+ HBSY = Zero
+ HIDX = Zero
+ Return (One)
+ }
+ Else
+ {
+ Return (Zero)
+ }
+ }
+}
diff --git a/src/mainboard/system76/lemp9/acpi/lid.asl b/src/mainboard/system76/lemp9/acpi/lid.asl
new file mode 100644
index 0000000000..729a0d9090
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/lid.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (LID0)
+{
+ Name (_HID, EisaId ("PNP0C0D"))
+ Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 })
+
+ Method (_LID, 0, NotSerialized) {
+ DEBUG = "LID: _LID"
+ If (^^PCI0.LPCB.EC0.ECOK) {
+ Return (^^PCI0.LPCB.EC0.LSTE)
+ } Else {
+ Return (One)
+ }
+ }
+
+ Method (_PSW, 1, NotSerialized) {
+ DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0))
+ If (^^PCI0.LPCB.EC0.ECOK) {
+ ^^PCI0.LPCB.EC0.LWKE = Arg0
+ }
+ }
+}
diff --git a/src/mainboard/system76/lemp9/acpi/mainboard.asl b/src/mainboard/system76/lemp9/acpi/mainboard.asl
new file mode 100644
index 0000000000..d065ee166e
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/mainboard.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB) {
+ #include "ac.asl"
+ #include "battery.asl"
+ #include "buttons.asl"
+ #include "hid.asl"
+ #include "lid.asl"
+ #include "s76.asl"
+ #include "sleep.asl"
+}
+
+Scope (_GPE) {
+ #include "gpe.asl"
+}
diff --git a/src/mainboard/system76/lemp9/acpi/s76.asl b/src/mainboard/system76/lemp9/acpi/s76.asl
new file mode 100644
index 0000000000..145feb0c72
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/s76.asl
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Notifications:
+// 0x80 - hardware backlight toggle
+// 0x81 - backlight toggle
+// 0x82 - backlight down
+// 0x83 - backlight up
+// 0x84 - backlight color change
+Device (S76D) {
+ Name (_HID, "17761776")
+ Name (_UID, 0)
+
+ Method (RSET, 0, Serialized) {
+ Debug = "S76D: RSET"
+ SAPL(0)
+ SKBL(0)
+ }
+
+ Method (INIT, 0, Serialized) {
+ Debug = "S76D: INIT"
+ RSET()
+ If (^^PCI0.LPCB.EC0.ECOK) {
+ // Set flags to use software control
+ ^^PCI0.LPCB.EC0.ECOS = 2
+ Return (0)
+ } Else {
+ Return (1)
+ }
+ }
+
+ Method (FINI, 0, Serialized) {
+ Debug = "S76D: FINI"
+ RSET()
+ If (^^PCI0.LPCB.EC0.ECOK) {
+ // Set flags to use hardware control
+ ^^PCI0.LPCB.EC0.ECOS = 1
+ Return (0)
+ } Else {
+ Return (1)
+ }
+ }
+
+ // Get Airplane LED
+ Method (GAPL, 0, Serialized) {
+ If (^^PCI0.LPCB.EC0.ECOK) {
+ If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
+ Return (1)
+ }
+ }
+ Return (0)
+ }
+
+ // Set Airplane LED
+ Method (SAPL, 1, Serialized) {
+ If (^^PCI0.LPCB.EC0.ECOK) {
+ If (Arg0) {
+ ^^PCI0.LPCB.EC0.AIRP |= 0x40
+ } Else {
+ ^^PCI0.LPCB.EC0.AIRP &= 0xBF
+ }
+ }
+ }
+
+ // Get KB LED
+ Method (GKBL, 0, Serialized) {
+ Local0 = 0
+ If (^^PCI0.LPCB.EC0.ECOK) {
+ ^^PCI0.LPCB.EC0.FDAT = One
+ ^^PCI0.LPCB.EC0.FCMD = 0xCA
+ Local0 = ^^PCI0.LPCB.EC0.FBUF
+ ^^PCI0.LPCB.EC0.FCMD = Zero
+ }
+ Return (Local0)
+ }
+
+ // Set KB Led
+ Method (SKBL, 1, Serialized) {
+ If (^^PCI0.LPCB.EC0.ECOK) {
+ ^^PCI0.LPCB.EC0.FDAT = Zero
+ ^^PCI0.LPCB.EC0.FBUF = Arg0
+ ^^PCI0.LPCB.EC0.FCMD = 0xCA
+ }
+ }
+}
diff --git a/src/mainboard/system76/lemp9/acpi/sleep.asl b/src/mainboard/system76/lemp9/acpi/sleep.asl
new file mode 100644
index 0000000000..9a3ecaa373
--- /dev/null
+++ b/src/mainboard/system76/lemp9/acpi/sleep.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+ \_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+ \_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
diff --git a/src/mainboard/system76/lemp9/board_info.txt b/src/mainboard/system76/lemp9/board_info.txt
new file mode 100644
index 0000000000..f6784eff02
--- /dev/null
+++ b/src/mainboard/system76/lemp9/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: lemp9
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/lemp9/bootblock.c b/src/mainboard/system76/lemp9/bootblock.c
new file mode 100644
index 0000000000..00c4588f5f
--- /dev/null
+++ b/src/mainboard/system76/lemp9/bootblock.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+
+void bootblock_mainboard_init(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/lemp9/data.vbt b/src/mainboard/system76/lemp9/data.vbt
new file mode 100644
index 0000000000..f14d8073e9
--- /dev/null
+++ b/src/mainboard/system76/lemp9/data.vbt
Binary files differ
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
new file mode 100644
index 0000000000..7a6ba6a959
--- /dev/null
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -0,0 +1,238 @@
+chip soc/intel/cannonlake
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+ # Disable s0ix
+ register "s0ix_enable" = "0"
+
+ # PM Timer Enabled
+ register "PmTimerDisabled" = "0"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+ # Power limit
+ register "tdp_pl1_override" = "15"
+ register "tdp_pl2_override" = "25"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable Enhanced Intel SpeedStep
+ register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+ register "SaGv" = "SaGv_Enabled"
+ #register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+ # SATA
+ register "SataMode" = "Sata_AHCI"
+ register "SataSalpSupport" = "0"
+
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsEnable[3]" = "0"
+ register "SataPortsEnable[4]" = "0"
+ register "SataPortsEnable[5]" = "0"
+ register "SataPortsEnable[6]" = "0"
+ register "SataPortsEnable[7]" = "0"
+
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[1]" = "0"
+ register "SataPortsDevSlp[2]" = "0"
+ register "SataPortsDevSlp[3]" = "0"
+ register "SataPortsDevSlp[4]" = "0"
+ register "SataPortsDevSlp[5]" = "0"
+ register "SataPortsDevSlp[6]" = "0"
+ register "SataPortsDevSlp[7]" = "0"
+
+ # Audio
+ register "PchHdaDspEnable" = "0"
+ register "PchHdaAudioLinkHda" = "1"
+ register "PchHdaAudioLinkDmic0" = "1"
+ register "PchHdaAudioLinkDmic1" = "1"
+ register "PchHdaAudioLinkSsp0" = "0"
+ register "PchHdaAudioLinkSsp1" = "0"
+ register "PchHdaAudioLinkSsp2" = "0"
+ register "PchHdaAudioLinkSndw1" = "0"
+ register "PchHdaAudioLinkSndw2" = "0"
+ register "PchHdaAudioLinkSndw3" = "0"
+ register "PchHdaAudioLinkSndw4" = "0"
+
+ # USB
+ register "SsicPortEnable" = "0"
+
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[4]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC
+
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # NC
+ register "usb3_ports[4]" = "USB3_PORT_EMPTY" # NC
+ register "usb3_ports[5]" = "USB3_PORT_EMPTY" # HSIO used by PCIe root port #6
+ register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC
+ register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC
+ register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC
+ register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC
+
+
+ # PCI Express root port #6 x1, Clock 3 (card reader)
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpLtrEnable[5]" = "1"
+ register "PcieClkSrcUsage[3]" = "5"
+ register "PcieClkSrcClkReq[3]" = "3"
+
+ # PCI Express root port #8 x1, Clock 2 (WLAN)
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpLtrEnable[7]" = "1"
+ register "PcieClkSrcUsage[2]" = "7"
+ register "PcieClkSrcClkReq[2]" = "2"
+
+ # PCI Express root port #9 x4, Clock 4 (SSD2)
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieClkSrcUsage[4]" = "8"
+ register "PcieClkSrcClkReq[4]" = "4"
+
+ # PCI Express root port #13 x4, Clock 5 (SSD1)
+ register "PcieRpEnable[12]" = "1"
+ register "PcieRpLtrEnable[12]" = "1"
+ register "PcieClkSrcUsage[5]" = "12"
+ register "PcieClkSrcClkReq[5]" = "5"
+
+ # Misc
+ register "Device4Enable" = "0"
+ register "HeciEnabled" = "0"
+ register "Heci3Enabled" = "0"
+ register "AcousticNoiseMitigation" = "1"
+ #register "dmipwroptimize" = "1"
+ #register "satapwroptimize" = "1"
+
+ # Power
+ register "PchPmSlpS3MinAssert" = "3" # 50ms
+ register "PchPmSlpS4MinAssert" = "1" # 1s
+ register "PchPmSlpSusMinAssert" = "2" # 500ms
+ register "PchPmSlpAMinAssert" = "4" # 2s
+
+ # Thermal
+ register "tcc_offset" = "12"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+ # LPC configuration from lspci -s 1f.0 -xxx
+ # Address 0x84: Decode 0x80 - 0x8F
+ register "gen1_dec" = "0x000c0081"
+ # Address 0x88: Decode 0x68 - 0x6F
+ register "gen2_dec" = "0x00040069"
+ # Address 0x8C: Decode 0x3320 - 0x332F
+ register "gen3_dec" = "0x000c3321"
+ # Address 0x90: Disabled
+ register "gen4_dec" = "0x00000000"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_WAKE_PIN"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+ register "gpe0_dw0" = "PMC_GPP_C"
+ register "gpe0_dw1" = "PMC_GPP_D"
+ register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 off end # SA Thermal device
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 13.0 off end # Integrated Sensor Hub
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ #chip drivers/intel/wifi
+ # register "wake" = "PME_B0_EN_BIT"
+ device pci 14.3 on end # CNVi wifi
+ #end
+ device pci 14.5 off end # SDCard
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 on end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 on end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 on end # PCI Express Port 13
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on end # LPC Interface
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 off end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl
new file mode 100644
index 0000000000..75a98885ed
--- /dev/null
+++ b/src/mainboard/system76/lemp9/dsdt.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/cannonlake/acpi/platform.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/cannonlake/acpi/southbridge.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Scope (\_SB.PCI0.LPCB)
+ {
+ #include <drivers/pc80/pc/ps2_controller.asl>
+ #include "acpi/ec.asl"
+ }
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h
new file mode 100644
index 0000000000..0d8737ad20
--- /dev/null
+++ b/src/mainboard/system76/lemp9/gpio.h
@@ -0,0 +1,547 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+#define PAD_CFG_NC(pad) PAD_NC(pad, NONE)
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+ // UART2
+ // UART2_RXD
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ // UART2_TXD
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ // NC
+ PAD_CFG_NC(GPP_C22),
+ // NC
+ PAD_CFG_NC(GPP_C23),
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+// GPD
+ // Power Management
+ // PM_BATLOW#
+ PAD_CFG_NC(GPD0),
+ // AC_PRESENT
+ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+ // NC
+ PAD_CFG_NC(GPD2),
+ // PWR_BTN#
+ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+ // SUSB#_PCH
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+ // SUSC#_PCH
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+ // SLP_A#
+ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+
+ // GPIO
+ // NC
+ PAD_CFG_NC(GPD7),
+
+ // Clock Signals
+ // SUS_CLK
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+
+ // Power Management
+ // GPD9_RTD3
+ PAD_CFG_NC(GPD9),
+ // NC
+ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+ // NC
+ PAD_CFG_NC(GPD11),
+
+// GPP_A
+ // LPC
+ // SB_KBCRST#
+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+ // LPC_AD0
+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+ // LPC_AD1
+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+ // LPC_AD2
+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+ // LPC_AD3
+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+ // LPC_FRAME#
+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+ // SERIRQ with pull up
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+
+ // GSPI0
+ // TODO - TPM_PIRQ#
+ PAD_CFG_NC(GPP_A7),
+
+ // LPC
+ // PM_CLKRUN# with pull-up
+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+ // PCLK_KBC
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+ // NC
+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+
+ // GSPI1
+ // INTP_OUT
+ _PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
+
+ // ISH_GP
+ // PCH_GPP_A12
+ PAD_CFG_NC(GPP_A12),
+
+ // Power Management
+ // SUSWARN#
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+
+ // LPC
+ // NC
+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+
+ // Power Management
+ // SUS_PWR_ACK
+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+
+ // SD
+ // NC
+ PAD_CFG_NC(GPP_A16),
+ // LIGHT_KB_DET#
+ PAD_CFG_NC(GPP_A17),
+
+ // ISH_GP
+ // NC
+ PAD_CFG_NC(GPP_A18),
+ // SATA_PWR_EN
+ PAD_CFG_GPO(GPP_A19, 1, DEEP),
+ // TEST_R
+ PAD_CFG_TERM_GPO(GPP_A20, 0, NONE, DEEP),
+ // NC
+ PAD_CFG_NC(GPP_A21),
+ // NC
+ PAD_CFG_NC(GPP_A22),
+ // NC
+ PAD_CFG_NC(GPP_A23),
+
+// GPP_B
+ // Power
+ // CORE_VID0
+ PAD_CFG_NC(GPP_B0),
+ // CORE_VID1
+ PAD_CFG_NC(GPP_B1),
+
+ // Power Management
+ // CNVI_WAKE#
+ PAD_CFG_NC(GPP_B2),
+
+ // CPU Misc
+ // GPP_B3
+ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000),
+ // NC
+ PAD_CFG_NC(GPP_B4),
+
+ // Clock Signals
+ // NC
+ PAD_CFG_NC(GPP_B5),
+ // NC
+ PAD_CFG_NC(GPP_B6),
+ // WLAN_CLKREQ#
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ // LAN_CLKREQ#
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+ // TBT_CLKREQ#
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ // SSD_CLKREQ#
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+
+ // Power Management
+ // EXT_PWR_GATE#
+ PAD_CFG_NC(GPP_B11),
+ // SLP_S0#
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ // PLT_RST#
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+ // SPKR
+ // PCH_SPKR
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+
+ // GSPI0
+ // NC
+ PAD_CFG_NC(GPP_B15),
+ // PCH_GPP_B16
+ PAD_CFG_NC(GPP_B16),
+ // PCH_GPP_B17
+ PAD_CFG_NC(GPP_B17),
+ // PCH_GPP_B18 - strap for disabling no reboot mode
+ PAD_CFG_NC(GPP_B18),
+
+ // GSPI1
+ // NC
+ PAD_CFG_NC(GPP_B19),
+ // NC
+ PAD_CFG_NC(GPP_B20),
+ // NC
+ PAD_CFG_NC(GPP_B21),
+ // PCH_GPP_B22
+ PAD_CFG_NC(GPP_B22),
+
+ // SMBUS
+ // NC
+ PAD_CFG_NC(GPP_B23),
+
+// GPP_C
+ // SMBUS
+ // SMB_CLK_DDR
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+ // SMB_DAT_DDR
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+ // PCH_GPP_C2 with pull-up
+ PAD_CFG_NC(GPP_C2),
+ // NC
+ PAD_CFG_NC(GPP_C3),
+ // NC
+ PAD_CFG_NC(GPP_C4),
+ // NC
+ PAD_CFG_NC(GPP_C5),
+ // LAN_WAKEUP#
+ PAD_CFG_NC(GPP_C6),
+ // NC
+ PAD_CFG_NC(GPP_C7),
+
+ // UART0
+ // NC
+ PAD_CFG_NC(GPP_C8),
+ // NC
+ PAD_CFG_NC(GPP_C9),
+ // TBT_FRC_PWR
+ PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
+ // NC
+ PAD_CFG_NC(GPP_C11),
+
+ // UART1
+ // GPP_C12_RTD3
+ PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
+ // SSD_PWR_DN#
+ PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
+ // TBTA_HRESET
+ PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
+ // NC
+ PAD_CFG_NC(GPP_C15),
+
+ // I2C
+ // T_SDA
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ // T_SCL
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ // NC
+ PAD_CFG_NC(GPP_C18),
+ // SWI
+ PAD_CFG_NC(GPP_C19),
+
+ // UART2
+ // UART2_RXD
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ // UART2_TXD
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ // NC
+ PAD_CFG_NC(GPP_C22),
+ // NC
+ PAD_CFG_NC(GPP_C23),
+
+// GPP_D
+ // SPI1
+ // NC
+ PAD_CFG_NC(GPP_D0),
+ // NC
+ PAD_CFG_NC(GPP_D1),
+ // NC
+ PAD_CFG_NC(GPP_D2),
+ // NC
+ PAD_CFG_NC(GPP_D3),
+
+ // IMGCLKOUT
+ // NC
+ PAD_CFG_NC(GPP_D4),
+
+ // I2C
+ // NC
+ PAD_CFG_NC(GPP_D5),
+ // NC
+ PAD_CFG_NC(GPP_D6),
+ // NC
+ PAD_CFG_NC(GPP_D7),
+ // SB_BLON
+ PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
+
+ // GSPI2
+ // SWI#
+ _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
+ // NC
+ PAD_CFG_NC(GPP_D10),
+ // BOARD_ID
+ PAD_CFG_NC(GPP_D11),
+ // PCH_GPP_D12
+ PAD_CFG_NC(GPP_D12),
+
+ // UART0
+ // GPP_D13_RTD3
+ PAD_CFG_TERM_GPO(GPP_D13, 1, NONE, PLTRST),
+ // SSD2_PWR_DN#
+ PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
+ // NC
+ PAD_CFG_NC(GPP_D15),
+ // RTD3_3G_PW R_EN
+ PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
+
+ // DMIC
+ // NC
+ PAD_CFG_NC(GPP_D17),
+ // NC
+ PAD_CFG_NC(GPP_D18),
+ // GPPC_DMIC_CLK
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+ // GPPC_DMIC_DATA
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+ // SPI1
+ // TPM_DET#
+ PAD_CFG_NC(GPP_D21),
+ // TPM_TCM_Detect
+ PAD_CFG_NC(GPP_D22),
+
+ // I2S
+ // NC
+ PAD_CFG_NC(GPP_D23),
+
+// GPP_E
+ // SATA
+ // PCH_GPP_E0 with pull-up
+ PAD_CFG_NC(GPP_E0),
+ // SATAGP1
+ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+ // SATAGP2
+ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
+
+ // CPU Misc
+ // NC
+ PAD_CFG_NC(GPP_E3),
+
+ // DEVSLP
+ // NC
+ PAD_CFG_NC(GPP_E4),
+ // DEVSLP1
+ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+ // DEVSLP2
+ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
+
+ // CPU Misc
+ // NC
+ PAD_CFG_NC(GPP_E7),
+
+ // SATA
+ // PCH_SATAHDD_LED#
+ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+ // USB2
+ // GP_BSSB_CLK
+ PAD_CFG_NC(GPP_E9),
+ // GPP_E10
+ PAD_CFG_NC(GPP_E10),
+ // GPP_E11
+ PAD_CFG_NC(GPP_E11),
+ // USB_OC#78
+ PAD_CFG_NC(GPP_E12),
+
+ // Display Signals
+ // MUX_HPD
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+ // HDMI_HPD
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+ // SMI#
+ _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0),
+ // SCI#
+ _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
+ // EDP_HPD
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+ // MDP_CTRLCLK
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+ // MDP_CTRLDATA
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+ // HDMI_CTRLCLK
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+ // HDMI_CTRLDATA
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+ // NC
+ PAD_CFG_NC(GPP_E22),
+ // NC
+ PAD_CFG_NC(GPP_E23),
+
+// GPP_F
+ // CNVI
+ // CNVI_GNSS_PA_BLANKING
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+
+ // GPIO
+ // NC
+ PAD_CFG_NC(GPP_F1),
+ // NC
+ PAD_CFG_NC(GPP_F2),
+ // NC
+ PAD_CFG_NC(GPP_F3),
+
+ // CNVI
+ // CNVI_BRI_DT
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+ // CNVI_BRI_RSP
+ PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
+ // CNVI_RGI_DT
+ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+ // CNVI_RGI_RSP
+ PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
+ // CNVI_MFUART2_RXD
+ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+ // CNVI_MFUART2_TXD
+ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+
+ // GPIO
+ // NC
+ PAD_CFG_NC(GPP_F10),
+
+ // EMMC
+ // NC
+ PAD_CFG_NC(GPP_F11),
+ // NC
+ PAD_CFG_NC(GPP_F12),
+ // NC
+ PAD_CFG_NC(GPP_F13),
+ // NC
+ PAD_CFG_NC(GPP_F14),
+ // NC
+ PAD_CFG_NC(GPP_F15),
+ // NC
+ PAD_CFG_NC(GPP_F16),
+ // NC
+ PAD_CFG_NC(GPP_F17),
+ // NC
+ PAD_CFG_NC(GPP_F18),
+ // NC
+ PAD_CFG_NC(GPP_F19),
+ // NC
+ PAD_CFG_NC(GPP_F20),
+ // NC
+ PAD_CFG_NC(GPP_F21),
+ // NC
+ PAD_CFG_NC(GPP_F22),
+
+ // A4WP
+ // A4WP_PRESENT
+ PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
+
+// GPP_G
+ // SD
+ // EDP_DET
+ PAD_CFG_NC(GPP_G0),
+ // NC
+ PAD_CFG_NC(GPP_G1),
+ // NC
+ PAD_CFG_NC(GPP_G2),
+ // ASM1543_I_SEL0
+ PAD_CFG_NC(GPP_G3),
+ // ASM1543_I_SEL1
+ PAD_CFG_NC(GPP_G4),
+ // BOARD_ID
+ PAD_CFG_NC(GPP_G5),
+ // NC
+ PAD_CFG_NC(GPP_G6),
+ // TBT_Detect
+ PAD_CFG_NC(GPP_G7),
+
+// GPP_H
+ // CNVI
+ // NC
+ PAD_CFG_NC(GPP_H0),
+ // CNVI_RST#
+ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
+ // CNVI_CLKREQ
+ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
+ // NC
+ PAD_CFG_NC(GPP_H3),
+
+ // I2C
+ // SMD_7411
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ // SMC_7411
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+ // NC
+ PAD_CFG_NC(GPP_H6),
+ // NC
+ PAD_CFG_NC(GPP_H7),
+ // NC
+ PAD_CFG_NC(GPP_H8),
+ // NC
+ PAD_CFG_NC(GPP_H9),
+
+ // I2C
+ // NC
+ PAD_CFG_NC(GPP_H10),
+ // NC
+ PAD_CFG_NC(GPP_H11),
+
+ // PCIE
+ // NC
+ PAD_CFG_NC(GPP_H12),
+ // NC
+ PAD_CFG_NC(GPP_H13),
+ // G_INT1
+ PAD_CFG_NC(GPP_H14),
+ // NC
+ PAD_CFG_NC(GPP_H15),
+
+ // Display Signals
+ // NC
+ PAD_CFG_NC(GPP_H16),
+ // NC
+ PAD_CFG_NC(GPP_H17),
+
+ // CPU Power
+ // CPU_C10_GATE#
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+
+ // TIMESYNC
+ // NC
+ PAD_CFG_NC(GPP_H19),
+
+ // IMGCLKOUT
+ // NC
+ PAD_CFG_NC(GPP_H20),
+
+ // GPIO
+ // GPPC_H21
+ PAD_CFG_NC(GPP_H21),
+ // TBT_RTD3_PWR_EN_R
+ PAD_NC(GPP_H22, NONE),
+ // NC, WIGIG_PEWAKE
+ PAD_CFG_NC(GPP_H23),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/system76/lemp9/hda_verb.c b/src/mainboard/system76/lemp9/hda_verb.c
new file mode 100644
index 0000000000..0539e89831
--- /dev/null
+++ b/src/mainboard/system76/lemp9/hda_verb.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* Realtek ALC293 */
+ 0x10ec0293, /* Vendor ID */
+ 0x15581401, /* Subsystem ID */
+ 12, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x15581401),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x41748245),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ /* Intel GPU HDMI */
+ 0x8086280b, /* Vendor ID */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of entries */
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/lemp9/ramstage.c b/src/mainboard/system76/lemp9/ramstage.c
new file mode 100644
index 0000000000..97d3dff10f
--- /dev/null
+++ b/src/mainboard/system76/lemp9/ramstage.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/lemp9/romstage.c b/src/mainboard/system76/lemp9/romstage.c
new file mode 100644
index 0000000000..6b9b02eb92
--- /dev/null
+++ b/src/mainboard/system76/lemp9/romstage.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+ /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+ .spd[0] = {
+ .read_type = READ_SPD_CBFS,
+ .spd_spec = {.spd_index = 0},
+ },
+ .spd[1] = {.read_type = NOT_EXISTING},
+ .spd[2] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa4},
+ },
+ .spd[3] = {.read_type = NOT_EXISTING},
+
+ /*
+ * For each channel, there are 3 sets of DQ byte mappings,
+ * where each set has a package 0 and a package 1 value (package 0
+ * represents the first 64-bit lpddr4 chip combination, and package 1
+ * represents the second 64-bit lpddr4 chip combination).
+ * The first three sets are for CLK, CMD, and CTL.
+ * The fsp package actually expects 6 sets, but the last 3 sets are
+ * not used in CNL, so we only define the three sets that are used
+ * and let the meminit_lpddr4() routine take care of clearing the
+ * unused fields for the caller.
+ */
+ .dq_map[DDR_CH0] = {
+ {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+ //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+ },
+ .dq_map[DDR_CH1] = {
+ {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+ //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+ },
+
+ /*
+ * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
+ * mapping of a dq bit on the CPU to the bit it's connected to on
+ * the memory part. The array index represents the dqs bit number
+ * on the memory part, and the values in the array represent which
+ * pin on the CPU that DRAM pin connects to.
+ */
+ .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+ .dqs_map[DDR_CH1] = {1, 0, 2, 3, 4, 5, 6, 7},
+
+ /*
+ * Rcomp resistor values. These values represent the resistance in
+ * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+ * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+ */
+ .rcomp_resistor = { 121, 81, 100 },
+
+ /*
+ * Rcomp target values. These will typically be the following
+ * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+ */
+ .rcomp_targets = { 100, 40, 20, 20, 26 },
+
+ /*
+ * Indicates whether memory is interleaved.
+ * Set to 1 for an interleaved design,
+ * set to 0 for non-interleaved design.
+ */
+ .dq_pins_interleaved = 1,
+
+ /*
+ * VREF_CA configuration.
+ * Set to 0 VREF_CA goes to both CH_A and CH_B,
+ * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+ * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+ */
+ .vref_ca_config = 2,
+
+ /* Early Command Training */
+ .ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}
diff --git a/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex b/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex
new file mode 100644
index 0000000000..f747f7c34e
--- /dev/null
+++ b/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex
@@ -0,0 +1,33 @@
+# Samsung K4AAG165WA-BCTD
+23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B
+0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36
+35 57 41 2D 42 43 54 44 20 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00