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-rw-r--r--src/commonlib/include/commonlib/timestamp_serialized.h4
-rw-r--r--src/cpu/intel/microcode/Kconfig2
-rw-r--r--src/drivers/intel/fsp1_1/exit_car.S2
-rw-r--r--src/drivers/intel/fsp2_0/Kconfig2
-rw-r--r--src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex2
-rw-r--r--src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex2
-rw-r--r--src/mainboard/hp/snb_ivb_laptops/Makefile.inc2
-rw-r--r--src/northbridge/intel/gm45/memmap.c4
-rw-r--r--src/northbridge/intel/i945/memmap.c4
-rw-r--r--src/northbridge/intel/pineview/memmap.c4
-rw-r--r--src/northbridge/intel/sandybridge/memmap.c4
-rw-r--r--src/northbridge/intel/x4x/memmap.c4
-rw-r--r--src/northbridge/intel/x4x/raminit_ddr23.c2
-rw-r--r--src/soc/intel/apollolake/glk_page_map.txt2
-rw-r--r--src/soc/intel/denverton_ns/Kconfig2
15 files changed, 21 insertions, 21 deletions
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index d7d636e6a4..ca72734df4 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -156,8 +156,8 @@ static const struct timestamp_id_to_name {
/* Marker to report base_time. */
{ 0, "1st timestamp" },
{ TS_START_ROMSTAGE, "start of romstage" },
- { TS_BEFORE_INITRAM, "before ram initialization" },
- { TS_AFTER_INITRAM, "after ram initialization" },
+ { TS_BEFORE_INITRAM, "before RAM initialization" },
+ { TS_AFTER_INITRAM, "after RAM initialization" },
{ TS_END_ROMSTAGE, "end of romstage" },
{ TS_START_VBOOT, "start of verified boot" },
{ TS_END_VBOOT, "end of verified boot" },
diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig
index 238aad745d..c7bbecbace 100644
--- a/src/cpu/intel/microcode/Kconfig
+++ b/src/cpu/intel/microcode/Kconfig
@@ -4,4 +4,4 @@ config MICROCODE_UPDATE_PRE_RAM
default y
help
Select this option if you want to update the microcode
- during the cache as ram setup.
+ during the cache as RAM setup.
diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S
index 4b2822a887..a8db68afd8 100644
--- a/src/drivers/intel/fsp1_1/exit_car.S
+++ b/src/drivers/intel/fsp1_1/exit_car.S
@@ -17,7 +17,7 @@
chipset_teardown_car:
pop %ebx
- /* Move the stack pointer to real ram */
+ /* Move the stack pointer to real RAM */
movl post_car_stack_top, %esp
/* Align the stack 16 bytes */
andl $0xfffffff0, %esp
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index a8b3ac43a5..2d45343083 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -61,7 +61,7 @@ config FSP_USE_REPO
and FSP_FD_PATH correctly so FSP splitting works.
config FSP_T_FILE
- string "Intel FSP-T (temp ram init) binary path and filename"
+ string "Intel FSP-T (temp RAM init) binary path and filename"
depends on FSP_CAR
default "$(obj)/Fsp_T.fd" if FSP_USE_REPO
help
diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex
index 111310a24a..f3e3e75ded 100644
--- a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex
+++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex
@@ -15,7 +15,7 @@
# GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E20XX has 2GB ram soldered down on the Q7
+# BAP ODE E20XX has 2GB RAM soldered down on the Q7
# Memory setting for DDR-1066
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex
index ba3d5ac4bf..6e90bfa92d 100644
--- a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex
+++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex
@@ -15,7 +15,7 @@
# GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E20XX has 2GB ram soldered down on the Q7
+# BAP ODE E20XX has 2GB RAM soldered down on the Q7
# Memory setting for DDR-800
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc
index d949ad8c05..50cea25914 100644
--- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc
+++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc
@@ -20,5 +20,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-# FIXME: Other variants with same size onboard ram may exist.
+# FIXME: Other variants with same size onboard RAM may exist.
SPD_SOURCES = hynix_4g
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index d34820eb3d..33abc510a1 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -133,8 +133,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of
- * ram to cover both cbmem as the TSEG region.
+ /* Cache 8 MiB region below the top of RAM and 2 MiB above top of
+ * RAM to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 54141205ec..83157d88ac 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -99,8 +99,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of
- * ram to cover both cbmem as the TSEG region.
+ /* Cache 8 MiB region below the top of RAM and 2 MiB above top of
+ * RAM to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 0aa70cdb34..9fde9f7fdb 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -149,8 +149,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of
- * ram to cover both cbmem as the TSEG region.
+ /* Cache 8 MiB region below the top of RAM and 2 MiB above top of
+ * RAM to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 6ebd7e0bb6..0784c11313 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -58,12 +58,12 @@ void fill_postcar_frame(struct postcar_frame *pcf)
top_of_ram = (uintptr_t)cbmem_top();
/* Cache 8MiB below the top of ram. On sandybridge systems the top of
- * ram under 4GiB is the start of the TSEG region. It is required to
+ * RAM under 4GiB is the start of the TSEG region. It is required to
* be 8MiB aligned. Set this area as cacheable so it can be used later
* for ramstage before setting up the entire RAM as cacheable. */
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
- /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems
+ /* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems
* is where the TSEG region resides. However, it is not restricted
* to SMM mode until SMM has been relocated. By setting the region
* to cacheable it provides faster access when relocating the SMM
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 1924ddf678..334e6c7a37 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -144,8 +144,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of
- * ram to cover both cbmem as the TSEG region.
+ /* Cache 8 MiB region below the top of RAM and 2 MiB above top of
+ * RAM to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index dd48d8ab63..1e871c7600 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1636,7 +1636,7 @@ static void set_dradrb(struct sysinfo *s)
dual_channel_size = MIN(size_ch0, size_ch1) * 2;
} else {
if (size_ch0 == 0) {
- /* ME needs ram on CH0 */
+ /* ME needs RAM on CH0 */
size_me = 0;
/* TOTEST: bailout? */
} else {
diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt
index e96a2db0ea..1a5f11fc0a 100644
--- a/src/soc/intel/apollolake/glk_page_map.txt
+++ b/src/soc/intel/apollolake/glk_page_map.txt
@@ -1,7 +1,7 @@
0x00000000, 0x100000000, WB, # RAM
# Above entry is needed because below 4G allocated memory range is
# only known after FSP memory init completes. However, FSP migrates to memory
-# from cache as ram before it exits FSP Memory Init. Hence we need to add
+# from cache as RAM before it exits FSP Memory Init. Hence we need to add
# page table entries for this entire range before FSP Memory Init. The
# overlapped MMIO ranges will be overridden by below entries.
0xd0000000, 0x100000000, UC, NX # All of MMIO
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index aed2beb3fd..9a611271ab 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -59,7 +59,7 @@ config MMCONF_BASE_ADDRESS
default 0xe0000000
config FSP_T_ADDR
- hex "Intel FSP-T (temp ram init) binary location"
+ hex "Intel FSP-T (temp RAM init) binary location"
depends on ADD_FSP_BINARIES && FSP_CAR
default 0xfff30000
help
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 09:33:10 +0000