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-rw-r--r--src/northbridge/intel/haswell/registers/mchbar.h2
-rw-r--r--src/northbridge/intel/sandybridge/registers/mchbar.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index a61036aca3..2dfad621f9 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -13,7 +13,7 @@
#define MC_INIT_STATE_G 0x5030
#define MRC_REVISION 0x5034 /* MRC Revision */
-#define MC_LOCK 0x50fc /* Memory Controlller Lock register */
+#define MC_LOCK 0x50fc /* Memory Controller Lock register */
#define GFXVTBAR 0x5400 /* Base address for IGD */
#define EDRAMBAR 0x5408 /* Base address for eDRAM */
diff --git a/src/northbridge/intel/sandybridge/registers/mchbar.h b/src/northbridge/intel/sandybridge/registers/mchbar.h
index 2fe6b24e76..d3df3c0d96 100644
--- a/src/northbridge/intel/sandybridge/registers/mchbar.h
+++ b/src/northbridge/intel/sandybridge/registers/mchbar.h
@@ -483,7 +483,7 @@
#define ECC_INJ_ADDR_COMPARE 0x5090 /* Address compare for ECC error inject */
#define ECC_INJ_ADDR_MASK 0x5094 /* Address mask for ECC error inject */
-#define MC_LOCK 0x50fc /* Memory Controlller Lock register */
+#define MC_LOCK 0x50fc /* Memory Controller Lock register */
#define GFXVTBAR 0x5400 /* Base address for IGD */
#define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */