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-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index d0006d64d7..60be8c9fab 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -175,6 +175,9 @@ chip soc/intel/cannonlake
register "tcc_offset" = "1"
+ # PCH Thermal Trip Temperature in deg C
+ register "common_soc_config.pch_thermal_trip" = "77"
+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {