diff options
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index af3d0cbeb8..53eb7120ae 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -18,6 +18,7 @@ #define __SOC_STONEYRIDGE_IOMAP_H__ /* MMIO Ranges */ +#define PSP_MAILBOX_BAR3_BASE 0xf0a00000 #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 19aaa4cbb8..18ef84c4fc 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -21,9 +21,15 @@ #include <types.h> #include <device/pci_ids.h> #include <device/device.h> +#include <device/pci_def.h> #include <soc/iomap.h> #include "chip.h" +/* PSP at D8F0 */ +#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ +#define PSP_BAR_ENABLES 0x48 +#define PSP_MAILBOX_BAR_EN 0x10 + /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 |