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-rw-r--r--src/mainboard/google/eve/gpio.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index deb0192111..d72b492c6b 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -104,9 +104,9 @@ static const struct pad_config gpio_table[] = {
/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
/* SM1DATA */ PAD_CFG_NC(GPP_C7),
/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
-/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */
+/* UART0_TXD */ PAD_CFG_GPI(GPP_C9, NONE, DEEP), /* FP_RST_ODL */
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */
+/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* PCH_FPS_MCU_BOOT0 */
/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
@@ -233,9 +233,9 @@ static const struct pad_config early_gpio_table[] = {
static const struct pad_config late_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
-/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */
+/* UART0_TXD */ PAD_CFG_GPI(GPP_C9, NONE, DEEP), /* FP_RST_ODL */
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */
+/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* PCH_FPS_MCU_BOOT0 */
};
#endif