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-rw-r--r--src/include/cpu/x86/tsc.h2
-rw-r--r--src/northbridge/intel/fsp_rangeley/udelay.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 8dd9b7519c..dd333e8930 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -11,8 +11,6 @@
#define TSC_SYNC
#endif
-#define MSR_PLATFORM_INFO 0xce
-
struct tsc_struct {
unsigned int lo;
unsigned int hi;
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c
index 01989abb37..08301a37f6 100644
--- a/src/northbridge/intel/fsp_rangeley/udelay.c
+++ b/src/northbridge/intel/fsp_rangeley/udelay.c
@@ -18,6 +18,8 @@
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#define MSR_PLATFORM_INFO 0xce
+
/**
* Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
*/